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| 型號(hào)： | MEA224AG |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA352 |
| 封裝： | 35 X 35 MM, 2.33 MM HEIGHT, PLASTIC, MS-034, BGA-352 |
| 文件頁(yè)數(shù)： | 6/29頁(yè) |
| 文件大?。?/td> | 519K |
| 代理商： | MEA224AG |
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PRELI
MI
NARY
D
A
TA
S
H
EET
XpressFlow-2001 Series –
EA-224
Ethernet Switch Chip-set
4-Port 10/100M Ethernet Access Controller
1997 Zarlink Semiconductor Inc.
Page: 13
Rev. 4.0 –December, 1997
4.2.5 Register Map
Note:
All 32-bit registers are D-word aligned.
All 16-bit registers are also D-word aligned and right justified.
For the Little Endian CPUs, register offset bit [1,0] are always set to be 00.
For the Big Endian CPUs, register offset bit [1,0] are always set to be 10.
? This is a Global Register. CPU is allowed to write the Global Register of all devices by a sin-
gle operation.
@ These registers are reserved for system diagnostic usage only.
I/O Offset
Register
Description
Little
Endian
Big
Endian
Reg.
Size
W/R
Note:
Device Configuration Registers (DCR)
GCRGlobal Control Register
hF00
hF02
16-bit
W/--
?
DCR0
Device Status Register
hF00
hF02
16-bit
--/R
DCR1
Signature & Revision Register
hF10
hF12
16-bit
--/R
DCR2
ID Register
hF20
hF22
16-bit
W/R
DCR3
Device Configuration Register
hF30
hF32
16-bit
W/R
DCR4
Interfaces Status Register
hF40
hF42
16-bit
--/R
DTSR
Test Register
hF70
hF72
16-bit
W/R
Interrupt Controls
ISR
Interrupt Status Register – Unmasked
hF80
hF82
16-bit
--/R
ISRM
Interrupt Status Register – Masked
hF90
hF92
16-bit
--/R
IMSK
Interrupt Mask Register
hFA0
hFA2
16-bit
W/R
IAR
Interrupt Acknowledgment Register
hFB0
hFB2
16-bit
W/--
Buffer Memory Interface
MWAR
Memory Write Address Reg. – Single Cycle
hE08
32-bit
W/R
MRAR
Memory Read Address Reg. – Single Cycle
hE18
32-bit
W/R
MBAR
Memory Address Register – Burst Mode
hE28
32-bit
W/R
MWBS
Memory Write Burst Size (in D-words)
hE40
hE42
16-bit
W/R
MRBS
Memory Read Burst Size (in D-words)
hE50
hE52
16-bit
W/R
MWDR
Memory Write Data Register
hE68
32-bit
W/--
MWDX
Memory Write Data Reg. – Byte Swapping
hE6C
32-bit
W/--
MRDR
Memory Read Data Register
hE68
32-bit
--/R
MRDX
Memory Read Data Reg. – Byte Swapping
hE6C
32-bit
--/R
FCB Buffer & Stack Management
FCBBA
Frame Control Buffer – Base Address
hD00
hD02
16-bit
W/R
FCBAG
Frame Control Buffer – Buffer Aging Status
hD30
hD32
16-bit
--/R
@
FCBSL
Frame Ctrl Buffer Stack – Size Limit
hD90
hD92
16-bit
W/R
FCBST
Frame Ctrl Buffer Stack – Buffer Low Threshold
hDA0
hDA2
16-bit
W/R
FCBSS
Frame Ctrl Buffer Stack – Allocation Status
hDB0
hDB2
16-bit
--/R
@
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