參數(shù)資料
型號(hào)： MF0640M-07AFxx
廠商： Mitsubishi Electric Corporation
英文描述： RESISTOR: 75.0K, 1/10W, 1%, PACKAGE 0805
中文描述： 16位產(chǎn)品數(shù)據(jù)總線閃存阿拉木圖PC卡
文件頁(yè)數(shù)： 3/32頁(yè)
文件大?。?/td> 211K
代理商： MF0640M-07AFXX
MITSUBISHI STORAGE CARD
Preliminary
ATA PC CARDS
MITSUBISHI
ELECTRIC
3
Oct.1999 Rev. 0.2
Signal Description
Signal Name
I/O
I
Pin No.
Description
Address bus[A10-A0]
8, 11, 12, 22,
23, 24, 25, 26,
27, 28, 29
41, 40, 39, 38,
37, 66, 65, 64,
6, 5, 4, 3,
2 ,32,31, 30
7, 42
Signals A10-A0 are address bus. A0 is invalid in
word mode. A10 is the MSB and A0 is the LSB.
Data bus[D15-D0]
I/O
Signals D15-D0 are data bus. D0 is the LSB of the
Even Byte of the Word. D8 is the LSB of the Odd Byte
of the Word.
Card Enable[CE1#, CE2#]
(PC Card Memory Mode)
Card Enable[CE1#, CE2#]
(PC Card I/O Mode)
Chip Select[CS0#, CS1#]
(IDE ATA Interface)
I
CE1# and CE2# are low active card select signals.
In IDE ATA Interface, CS0# is used to select the
Command Block Registers. CS1# is used to select
the Control Block Registers.
OE# is used to gate Attribute and Common Memory
Read data from the ATA Card.
OE# is used to gate Attribute Memory Read data
from the ATA Card.
To enable IDE ATA Interface, this input should be
grounded by the host.
WE# is used for strobing Attribute and Common
Memory Write data into the ATA Card.
WE# is used for strobing Attribute Memory Write
data into the ATA Card.
This input should be connected Vcc by the host.
Output Enable[OE#]
(PC Card Memory Mode)
Output Enable[OE#]
(PC Card I/O Mode)
ATA SEL#
(IDE ATA Interface)
Write Enable[WE#]
(PC Card Memory Mode)
Write Enable[WE#]
(PC Card I/O Mode)
Write Enable[WE#]
(IDE ATA Interface)
I/O Read[IORD#]
(PC Card I/O Mode)
I/O Read[IORD#]
(IDE ATA Interface)
I/O Write[IOWR#]
(PC Card I/O Mode)
I/O Write[IOWR#]
(IDE ATA Interface)
Ready[READY]
(PC Card Memory Mode)
IREQ#
(PC Card I/O Mode)
I
9
I
15
I
44
IORD# is used to read data from the Card’s I/O
space.
I
45
IOWR# is used to write data to the Card’s I/O space.
O
16
READY signal is set high when the ATA Card is
ready to accept a new data transfer operation.
This signal of low level is indicates that the card is
requesting software service to host, and high level
indicates that the card is not requesting.
This signal is active high interrupt request to the
host.
CD1# and CD2# provided for proper detection of PC
Card insertion.
This signal is held low because this card does not
have a write protect switch.
This output signal is asserted when the I/O port
address is capable of 16-bit access.
INTRQ
(IDE ATA Interface)
Card Detection[CD1#, CD2#]
O
36, 67
Write Protect[WP]
(PC Card Memory Mode)
IOIS16#
(PC Card I/O Mode)
IOCS16#
(IDE ATA Interface)
O
33
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PDF描述
MF0640M-07BFxx 8/16-bit Data Bus Flash ATA PC Card
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