參數(shù)資料
型號: MF1S5030DA8
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: MIFARE Classic 1K - Mainstream contactless smart card IC for fast and easy solution development
封裝: MF1S5030DA3<SOT500|<<<1<Always Pb-free,;MF1S5030DA4<SOT500-2 (PLLMC)|<<http://www.nxp.com/packages/SOT500-2.html<1<Always Pb-free,;MF1S5030DA6<SOT500-3 (PLLMC)|&
文件頁數(shù): 36/37頁
文件大小: 425K
代理商: MF1S5030DA8
MF1S503x
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.1 — 21 February 2011
194031
36 of 37
NXP Semiconductors
MF1S503x
MIFARE Classic 1K - Mainstream contactless smart card IC
21. Tables
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3
Table 3. Pin allocation table . . . . . . . . . . . . . . . . . . . . . . .4
Table 4. Memory operations. . . . . . . . . . . . . . . . . . . . . .11
Table 5. Access conditions. . . . . . . . . . . . . . . . . . . . . . .11
Table 6. Access conditions for the sector trailer . . . . . .12
Table 7. Access conditions for data blocks. . . . . . . . . . .13
Table 8. Command overview . . . . . . . . . . . . . . . . . . . . .14
Table 9. MIFARE ACK and NAK . . . . . . . . . . . . . . . . . .15
Table 10. ATQA response of the MF1S503x . . . . . . . . . .15
Table 11. SAK response of the MF1S503x . . . . . . . . . . .15
Table 12. MIFARE authentication command . . . . . . . . . .16
Table 13. MIFARE authentication timing . . . . . . . . . . . . .17
Table 14. MIFARE Read command . . . . . . . . . . . . . . . . .17
Table 15. MIFARE Read timing . . . . . . . . . . . . . . . . . . . .17
Table 16. MIFARE Write command . . . . . . . . . . . . . . . . .18
Table 17. MIFARE Write timing . . . . . . . . . . . . . . . . . . . . 19
Table 18. MIFARE Increment, Decrement and
Restore command . . . . . . . . . . . . . . . . . . . . . . 20
Table 19. MIFARE Increment, Decrement and
Restore timing . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 20. MIFARE Transfer command. . . . . . . . . . . . . . . 21
Table 21. MIFARE Transfer timing. . . . . . . . . . . . . . . . . . 21
Table 22. Limiting values
[1][2]
. . . . . . . . . . . . . . . . . . . . . 22
Table 23. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 24. Wafer specifications MF1S5035DUx/L . . . . . . 23
Table 25. Wafer specifications MF1S5037DUx . . . . . . . 23
Table 26. Bond pad specifications. . . . . . . . . . . . . . . . . . 24
Table 27. Bump specifications. . . . . . . . . . . . . . . . . . . . . 24
Table 28. Abbreviations and symbols . . . . . . . . . . . . . . . 31
Table 29. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 33
22. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. Frame Delay Time (from PCD to PICC)
and T
ACK
and T
NAK
. . . . . . . . . . . . . . . . . . . . . . . .15
Fig 11. MIFARE Authentication part 1 . . . . . . . . . . . . . . .16
Fig 12. MIFARE Authentication part 2 . . . . . . . . . . . . . . .16
Fig 13. MIFARE Read . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Fig 14. MIFARE Write part 1 . . . . . . . . . . . . . . . . . . . . . .18
Fig 15. MIFARE Write part 2 . . . . . . . . . . . . . . . . . . . . . .18
Fig 16. MIFARE Increment, Decrement,
Restore part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Fig 17. MIFARE Increment, Decrement,
Restore part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Fig 18. MIFARE Transfer . . . . . . . . . . . . . . . . . . . . . . . . .20
Fig 19. Package outline SOT500-2 . . . . . . . . . . . . . . . . .26
Fig 20. Package outline SOT500-3 . . . . . . . . . . . . . . . . .27
Fig 21. Package outline SOT500-4 . . . . . . . . . . . . . . . . .28
Fig 22. Bare die outline and chip orientation
MF1S5035 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Fig 23. Bare die outline and chip orientation
MF1S5037 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
MIFARE card reader . . . . . . . . . . . . . . . . . . . . . . .1
Block diagram of MF1S503x . . . . . . . . . . . . . . . . .3
Pin configuration for SOT500-2 (MOA4) . . . . . . . .4
Three pass authentication . . . . . . . . . . . . . . . . . . .6
Memory organization . . . . . . . . . . . . . . . . . . . . . . .8
Manufacturer block . . . . . . . . . . . . . . . . . . . . . . . .9
Value blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Sector trailer . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Access conditions . . . . . . . . . . . . . . . . . . . . . . . .12
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