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參數(shù)資料
| 型號(hào)： | MGCM02BP1N |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | TDMA/AMPS IF and Baseband Interface |
| 中文描述： | 時(shí)分多址/ AMPS二元IF和基帶接口 |
| 文件頁(yè)數(shù)： | 17/21頁(yè) |
| 文件大?。?/td> | 529K |
| 代理商： | MGCM02BP1N |
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Data Sheet
MGCM02
17
Lock Detect Output Polarity
The Lock detect output polarity can be inverted using
RLI, TLI - Word3 Bits 18,19. In normal operation lock
detect outputs are high when locked.
Lock Detect Output Control
The receive or transmit lock detect output can be
selected for gating with the UHF lock detect input
using the LDC bit - Word 5 Bit 5. The gating for the
total lock detect function is shown below. The RLI
and TLI bits should be set to 0. The combined lock
detect output is available on Pin 38
MGCM02 Power Control
MGCM02 features
fl
exible power control using the
PCS<2:0> Word 7 - Bits 17:15 using the serial bus in
conjunction with the PCA pin.
Description of Power Control Modes
Deep Sleep
- In this mode all circuitry is powered
down except the power control circuits.
Powerdown
- As deep sleep but voltage reference
circuits active. PLL and VCO circuit can still be active
(see TX,RX PLL ON modes)
RX
- Receive Channel powered on. Operates in
conjunction with RX mode control.
TX
- Transmit Channel powered on. Operates in
conjunction with TX mode control.
Duplex
- Receive and Transmit channels active.
Alt RX/TX
- Receive and transmit under control of
the PCA control. Receive on when PCA = 0, Transmit
on when PCA = 1
RSSI on.
RSSI circuitry is activated when receive
mode subsequently selected. This mode must be
RTC, TTC
Mode
0
Normal
1
Tristate
RLI, TLI
Mode
0
Normal
1
Invert
UHF
LOCK
RX/TX
LOCK
LOCK
DET
Mode
0
X
0
UHF Unlocked
1
0
0
UHF Locked, Rx or Tx
Unlocked
1
1
1
All PLLs Locked
PCS <3:0>
Mode
0
0
0
0
Deep Sleep
0
1
0
0
Standby
0
0
1
0
TX
0
1
1
0
RX
0
0
0
1
Duplex
0
1
0
1
Alt Rx/Tx
0
0
1
1
RSSI On
0
1
1
1
RSSI Off
1
0
0
0
TX PLL ON
1
1
0
0
TX PLL OFF
1
0
1
0
RX PLL ON
1
1
1
0
RX PLL OFF
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