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參數(shù)資料
| 型號： | MGCM02BP1Q |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | TDMA/AMPS IF and Baseband Interface |
| 中文描述： | 時分多址/ AMPS二元IF和基帶接口 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 529K |
| 代理商： | MGCM02BP1Q |
MGCM02
Data Sheet
2
Pad Assignment
No
Pin Name
Type
Description
A1
RTUNE
Bias Reference - connect 100k
to ground
A2
VBG
Bandgap Reference Decoupling
A3
PCA
Input
Power Control Assert
A4
SDATA
Input
Serial Interface, Serial Data In
A5
VDD
Power
Power Supply - Digital
A6
TCXO
Input
19.44MHz Reference from TCXO
A7
GND (TX)
Ground
Ground - Transmit Section
B1
RXI OP+
Output
Baseband Receive I Output +
B2
RXI OP-
Output
Baseband Receive I Output -
B3
SCLK
Input
Serial Interface, Clock
B4
GND
Input
Ground Digital
B5
RESETB
Input
Reset (active low)
B6
TXQ IP-
Input
Transmit Q Input -
B7
TXQ IP+
Input
Transmit Q Input +
C1
RXQ OP-
Output
Baseband Receive Q Output -
C2
GND
Ground
Ground - Receive Section
C3
AGC
Input
AGC control voltage
C4
SLATCH
Input
Serial Interface, Latch
C5
LOCK DET
Output
Synthesiser Lock Detect
C6
TXI IP-
Input
Transmit I Input -
C7
TXI IP+
Input
Transmit I Input +
D1
RX IP+
Input
Receive IF Input +
D2
RXQ OP+
Output
Baseband Receive Q Output +
D3
GND
Ground
Ground (Substrate Connection)
D4
NC
Not Connected
D5
GND
Ground
Ground (Substrate Connection)
D6
TXI OP+
Output
Transmit I Output +
D7
VDD
Power
Power Supply - Transmit Section
E1
RX IP-
Input
Receive IF Input -
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