參數(shù)資料
型號(hào)： MH16S72DDFA-8
廠商： Mitsubishi Electric Corporation
英文描述： 1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
中文描述： 1207959552位（16,777,216字72位）同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁(yè)數(shù)： 20/52頁(yè)
文件大小： 1045K
代理商： MH16S72DDFA-8
MH16S72AMA -8,-10,-12
1207959552-BIT (16777216 - WORD BY 72-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 52 )
20
MITSUBISHI
ELECTRIC
5. Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0128-0.0
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read option can be interrupted by new read of the same or the other bank.
MH16S72AMA allows random column access. READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=3)
CK
Command
A10
DQ
READ
Yi
0
0
READ
Yk
0
1
Qai0
Qaj1 Qbk0 Qbk1
READ
Yj
0
0
Qaj0
Qbk2
Qal0
READ
Yl
0
0
Qal1
Qal2
Qal3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of the same or the other bank. Random
column access is allowed. In this case, the DQ should be controlled adequately by using the
DQMB0-7 to prevent the bus contention. The output is disabled automatically 2 cycle after
WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CK
Command
A10
Q
READ
Yi
0
0
Qai0
Write
Yj
0
0
D
Daj0
Daj1
Daj2
Daj3
DQMB0-7
DQM control
Write control
A0-9,11
BA0,1
A0-9,11
BA0,1
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