參數(shù)資料
型號(hào): MH16S72DDFA-8
廠商: Mitsubishi Electric Corporation
英文描述: 1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
中文描述: 1207959552位(16,777,216字72位)同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁(yè)數(shù): 31/52頁(yè)
文件大?。?/td> 1045K
代理商: MH16S72DDFA-8
MH16S72AMA -8,-10,-12
1207959552-BIT (16777216 - WORD BY 72-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 52 )
31
MITSUBISHI
ELECTRIC
5. Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0128-0.0
Max.
AC TIMING REQUIREMENTS
(SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Limits
-10
Min.
15
Symbol Parameter
-12
Unit
Max.
Min.
Max.
tCLK
CK cycle time
15
ns
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tPDE
tREF
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Mode Register Set Cycle time
Power Down Exit time
Refresh Interval time
4
4
1
3
1
10
4
4
1
3
1
10
10
90
30
60 10000
30
10
20
20
10
100
30
70 10000
30
12
24
24
12
64
64
CK
Signal
1.4V
1.4V
Any AC timing is
referenced to the input
signal crossing through
1.4V.
CL=2
CL=3
Min.
12
-8
3
3
1
2
1
8
10
80
24
56 10000
24
10
16
16
8
64
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