參數(shù)資料
型號: MH28S72PJG-7
廠商: Mitsubishi Electric Corporation
英文描述: KPSE 19C 19#20 SKT RECP
中文描述: 9663676416位(134217728 - Word的72位)同步動態(tài)隨機存儲器
文件頁數(shù): 1/57頁
文件大?。?/td> 954K
代理商: MH28S72PJG-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MH28S72PJG -5,-6,-7
27/Mar. /2001
MIT-DS-406-0.2
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
DESCRIPTION
APPLICATION
Main memory unit for computers, Microcomputer memory.
FEATURES
Utilizes industry standard 64M X 4 Synchronous DRAMs in
TSOP package , industry standard Resister in TSSOP package ,
and industry standard PLL in TSSOP package.
Single 3.3V +/- 0.3V supply
Burst length 1/2/4/8/Full Page (programmable)
Burst type sequential / interleave (programmable)
Column access random
Burst W rite / Single Write (programmable)
Auto precharge / Auto bank precharge controlled by A10
Auto refresh and Self refresh
LVTTL Interface
8192 refresh cycles every 64ms
1
1pin
10pin
11pin
40pin
41pin
84pin
85pin
94pin
95pin
124pin
125pin
168pin
The MH28S72PJG is 134,217,728 - word x 72-bit
Synchronous DRAM stacked structural module. This
consist of thirty-six industry standard 64M x 4
Synchronous DRAMs in TSOP.
The stacked structure of TSOP on a card edge dual in-
line package provides any application where high
densities and large of quantities memory are required.
This is a socket-type memory module ,suitable for
easy interchange or addition of module.
Frequency
CLK Access Time
(at Latch mode,Components)
100MHz
6.0ns(CL=3)
-7
133MHz
5.4ns(CL=4)
-6
-5
5.4ns(CL=3)
133MHz
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