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參數(shù)資料
| 型號： | MH28S72PJG-7 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | KPSE 19C 19#20 SKT RECP |
| 中文描述： | 9663676416位（134217728 - Word的72位）同步動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 53/57頁 |
| 文件大?。?/td> | 954K |
| 代理商： | MH28S72PJG-7 |
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9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table I
Byte
Function described
0
Defines # bytes written into serial memory at module mfgr
1
Total # bytes of SPD memory device
2
Fundamental memory type
3
# Row Addresses on this assembly
4
# Column Addresses on this assembly
5
# Module Banks on this assembly
6
Data Width of this assembly...
7
... Data Width continuation
8
Voltage interface standard of this assembly
9
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
-7
MH28S72PJG -5,-6,-7
27/Mar. /2001
MIT-DS-406-0.2
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
53
SPD enrty data
128
256 Bytes
SDRAM
A0-A12
SPD DATA(hex)
80
08
04
0D
A0-A9,11
2BANK
0B
02
x72
0
LVTTL
7.5ns
48
00
01
75
A0
54
10
SDRAM Access from Clock
tAC for CL=3
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
6ns
60
11
12
13
14
15
16
17
18
ECC
02
82
self refresh(7.8uS)
SDRAM width,Primary DRAM
Error Checking SDRAM data width
x4
x4
04
04
01
8F
04
Minimum Clock Delay,Back to Back Random Column Addresses
1
Burst Lengths Supported
1/2/4/8/Full page
# Banks on Each SDRAM device
CAS# Latency
4bank
2/3
19
20
21
22
CS# Latency
Write Latency
0
0
01
01
1F
SDRAM Module Attributes
SDRAM Device Attributes:General
Precharge All,Auto precharge
7.5ns
0E
75
23
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
24
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
25
26
SDRAM Cycle time(3rd highest CAS latency)
N/A
00
N/A
15ns
00
0F
SDRAM Access form Clock(3rd highest CAS latency)
27
Precharge to Active Minimum
28
Row Active to Row Active Min.
15ns
20ns
0F
14
10ns
5.4ns
-7
10ns
A0
6ns
60
-7
29
RAS to CAS Delay Min
30
Active to Precharge Min
50ns
32
-5,-6
-7
-5,-6
06
-6
10ns
A0
-6
5.4ns
54
-6,-7,
20ns
14
-7
-5,-6
-6,-7
-7
-5.-6
20ns
45ns
14
2D
buffered,registered
-5
-5
6ns
60
-5
15ns
0F
-5
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| MH2M365CXJ-5 | HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM |
| MH2M365CNXJ-5 | HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM |
| MH2M365CNXJ-6 | HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM |
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| MH2M365CXJ-7 | HYPER PAGE MODE 75497472-BIT ( 2097152-WORD BY 36-BIT ) DYNAMIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH28TAD | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
| MH28TAD-R | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
| MH28TAG | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
| MH28TAG-R | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
| MH28TBD | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
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