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參數(shù)資料
| 型號： | MH2S64CWXTJ-15 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
| 中文描述： | 134217728位（2097152字，64位）SynchronousDRAM |
| 文件頁數(shù)： | 26/45頁 |
| 文件大?。?/td> | 691K |
| 代理商： | MH2S64CWXTJ-15 |
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MH2S64CZTJ/CWZTJ-12,-15,-1539
134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( 26
MITSUBISHI
ELECTRIC
Oct.28.1996
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0019-0.4
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK
suspend is power down, output suspend or input suspend. CKE is a synchronous
input except during the self-refresh mode. CLK suspend can be performed either
when the banks are active or idle, but a command at the following cycle is ignored.
CK
(ext.CLK)
CKE
int.CLK
Power Down by CKE
CK
Command
PRE
CKE
Command
CKE
ACT
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Standby Power Down
Active Power Down
NOP
NOP
DQ Suspend by CKE
CK
Command
DQ
Write
D0
D1
D2
D3
CKE
READ
Q0
Q1
Q2
Q3
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| MH2S64CWXTJ-1539 | 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH2S64CWXTJ-1539 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
| MH2S64CWZTJ-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
| MH2S64CWZTJ-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
| MH2S64CWZTJ-1539 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
| MH2S64CZTJ-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
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