參數(shù)資料
型號： MH32D64AKQJ-10
廠商： Mitsubishi Electric Corporation
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:56; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:24; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:24-4 RoHS Compliant: No
中文描述： 2147483684位（33554432字64位），雙數(shù)據(jù)速率同步DRAM模塊
文件頁數(shù)： 36/40頁
文件大?。?/td> 350K
代理商： MH32D64AKQJ-10
MH32D64KQH-75,-10
2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0417-0.2
17.May.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
36
Serial Presence Detect Table I
Byte
Function described
SPD enrty data
SPD DATA(hex)
0
Number of Serial PD Bytes Written during Production
128
80
1
Total # bytes of SPD memory device
256 Bytes
08
2
Fundamental memory type
SDRAM DDR
07
0D
0A
3
# Row Addresses on this assembly
13
4
# Column Addresses on this assembly
10
5
# Module Banks on this assembly
1BANK
01
6
Data Width of this assembly...
x64
0
40
7
... Data Width continuation
00
8
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
SSTL2.5V
7.5ns
04
75
80
9
Cycle time for CL=2.5
10
SDRAM Access from Clock
tAC for CL=2.5
11
DIMM Configuration type (Non-parity,Parity,ECC)
None-parity,Non-ECC
00
82
12
Refresh Rate/Type
13
SDRAM width,Primary DRAM
x8
08
14
Error Checking SDRAM data width
MIimum Clock Delay, Random Column Access
N/A
00
15
01
16
Burst Lengths Supported
Number of Device Banks
2, 4, 8
0E
04
0C
17
4bank
2.0, 2.5
0
18
CAS# Latency
19
CS# Latency
20
WE Latency
21
SDRAM Module Attributes
20
22
SDRAM Device Attributes:General
VDD + 0.2V
00
23
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
24
SDRAM Access form Clock(2nd highest CAS latency)
80
tAC for CL=2
25
SDRAM Cycle time(3rd highest CAS latency)
26
SDRAM Access form Clock(3rd highest CAS latency)
27
Minimum Row Precharge Time (tRP)
15ns
50
28
Minimum Row Active to Row Active Delay (tRRD)
20ns
3C
8.0ns
-10
10ns
A0
75
-75
29
RAS to CAS Delay Minv (tRCD)
20ns
2D
30
Active to Precharge Min (tRAS)
32
+0.75ns
+0.8 ns
-75
-10
-75
-10
-75
-10
-75
-10
45ns
50ns
+0.75ns
+0.8ns
Differential Clock
75
80
00
50
7.8uS/SR
1
02
01
1 clock
10ns
A0
-75
-10
-75
-10
Undefined
Undefined
Undefined
Undefined
00
00
00
相關(guān)PDF資料
PDF描述
MH32D64AKQJ-75 Circular Connector; No. of Contacts:61; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:24; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:24-61 RoHS Compliant: No
MH32D64KQH-10 2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MH32D72AKLA-10 JT 53C 53#22 SKT GRND PLUG
MH32D72AKLA-75 Circular Connector; No. of Contacts:79; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:20-35 RoHS Compliant: No
MH32D72AKLB-10 JT 79C 79#22D SKT GRND PLUG
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MH32D64AKQJ-75 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,147,483,684-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MH32D64KQH-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MH32D64KQH-75 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MH32D72AKLA-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MH32D72AKLA-75 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
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