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參數(shù)資料
| 型號： | MH32D64KQH-10 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module |
| 中文描述： | 2147483648位（33554432字64位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 1/40頁 |
| 文件大?。?/td> | 350K |
| 代理商： | MH32D64KQH-10 |
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MH32D64KQH-75,-10
2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0417-0.2
17.May.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
1
DESCRIPTION
APPLICATION
Main memory unit for Note PC, Mobile etc.
FEATURES
Type name
133MHz
MH32D64KQH-10
MH32D64KQH-75
Max.
Frequency
100MHz
The MH32D64KQH is 33554432 - word x 64-bit Double
Data Rate(DDR) Synchronous DRAM mounted module.
This consists of 8 industry standard 32M x 8 DDR
Synchronous DRAMs in TSOP with SSTL_2 interface which
achieves very high speed data rate up to 133MHz.
This socket-type memory module is suitable for main
memory in computer systems and easy to interchange or
add modules.
CLK
Access Time
[component level]
+ 0.75ns
+ 0.8ns
(Front)
(Back)
1
2
199
200
PCB Outline
-
Utilizes industry standard 32M X 8 DDR Synchronous DRAMs
in TSOP package , industry standard EEPROM(SPD) in
TSSOP package
-
200pin SO-DIMM
-
Vdd=Vddq=2.5v±0.2V
- Double data rate architecture; two data transfers per
clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received
with data
- Differential clock inputs (CLK and /CLK)
-
DLL aligns DQ and DQS transitions with CLK transition edges of DQS
- Commands entered on each positive CLK edge
- Data and data mask referenced to both edges of DQS
- 4bank operation concontrolled byBA0,BA1(Bank Address
,discrete)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst Type - sequential/interleave(programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9
- SSTL_2 Interface
- Module 1bank Configration
相關PDF資料 |
PDF描述 |
|---|---|
| MH32D72AKLA-10 | JT 53C 53#22 SKT GRND PLUG |
| MH32D72AKLA-75 | Circular Connector; No. of Contacts:79; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:20-35 RoHS Compliant: No |
| MH32D72AKLB-10 | JT 79C 79#22D SKT GRND PLUG |
| MH32D72AKLB-75 | Circular Connector; No. of Contacts:41; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:20-41 RoHS Compliant: No |
| MH32D72KLH-10 | 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MH32D64KQH-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module |
| MH32D72AKLA-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH32D72AKLA-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH32D72AKLB-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH32D72AKLB-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
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