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參數(shù)資料
| 型號： | MH32D72AKLA-75 |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:79; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:20-35 RoHS Compliant: No |
| 中文描述： | 2415919104位（33554432 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 23/38頁 |
| 文件大?。?/td> | 327K |
| 代理商： | MH32D72AKLA-75 |
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH32D72AKLA-10,-75
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0398-1.1
24.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
23
READ
After tRCD from the bank activation, a READ command can be issued. 1st Output data is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the
Burst Length is BL. The start address is specified by A11,A9-A0, and the address sequence of burst data
is defined by the Burst Type. A READ command may be applied to any active bank, so the row
precharge time (tRP) can be hidden behind continuous output data by interleaving the
multiple banks. When A10 is high at a READ command, the auto-precharge(READA) is
performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at BL/2 after READA. The next ACT
command can be issued after (BL/2+tRP) from the previous READA.
Multi Bank Interleaving READ (BL=8, CL=2(Discrete level))
/CLK
CLK
Command
A0-9,11
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
READ
Y
0
10
ACT
Xb
Xb
10
PRE
0
00
tRCD
Burst Length
DQS
Qa0
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
Qa7 Qb0
Qb1
Qb2
Qb3
Qb4
Qb5
Qb7
Qb8
Module /CAS latency(Discrete CL + 1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MH32D72AKLB-10 | JT 79C 79#22D SKT GRND PLUG |
| MH32D72AKLB-75 | Circular Connector; No. of Contacts:41; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:20-41 RoHS Compliant: No |
| MH32D72KLH-10 | 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH32D72KLH-75 | 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH32S72AQJA-7 | ER 3C 3#16S PIN RECP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH32D72AKLB-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH32D72AKLB-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH32D72KLH-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH32D72KLH-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH32FAD | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
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