參數(shù)資料
型號(hào): MH4S64BBKG-7
廠商: Mitsubishi Electric Corporation
英文描述: 268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
中文描述: 268435456位(4194304 -文字,64位)SynchronousDRAM
文件頁(yè)數(shù): 32/55頁(yè)
文件大?。?/td> 586K
代理商: MH4S64BBKG-7
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
32
MITSUBISHI
ELECTRIC
29.Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.5
1.4V
1.4V
DQ
CK
tAC
tOH
tOHZ
SWITCHING CHARACTERISTICS
(SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise note3)
Output Load
Condition
V
OUT
50pF
50
V
TT
=1.4V
DQ
CK
Output Timing
Measurement
Reference Point
1.4V
1.4V
V
REF
=1.4V
Note:3 If tr(clock rising time) is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Limits
-8
Min.
Symbol Parameter
Unit
Max.
tAC
Access time from CK
7
ns
tOH
Output Hold time
from CK
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
3
ns
tOLZ
0
ns
tOHZ
3
ns
6
-7
Min.
6
3
0
3
6
Max.
6
6
ns
CL=2
CL=3
-10
Min.
Max.
8
3
0
3
8
8
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