參數(shù)資料
型號: MH4S64CBMD-12B
廠商: Mitsubishi Electric Corporation
英文描述: 268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
中文描述: 268435456位(4194304字,64位)SynchronousDRAM
文件頁數(shù): 14/55頁
文件大?。?/td> 586K
代理商: MH4S64CBMD-12B
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
14
MITSUBISHI
ELECTRIC
29.Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.5
DQ
Command
Address
CK
ACT
X
Q0
Q1
Q2
Q3
Y
DQ
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK frequency,i.e.,the
speed of CLK determines which CL should be used.First output data is available after CL
cycles from READ command.
/CAS Latency Timing(BL=4)
READ
tRCD
CL=2
Q0
Q1
Q2
Q3
CL=3
CL=2
CL=3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be
automatically performed after the initial write or read command.For BL=1,2,4,8,full page the
output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst
Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2)
tRCD
DQ
Command
Address
CK
ACT
X
Y
DQ
READ
DQ
DQ
DQ
Q0
Q1
Q2
Q3
Q5
Q6
Q4
Q7
Q8
Q0
Q1
Q2
Q3
Q5
Q6
Q4
Q7
Q0
Q1
Q2
Q3
Q0
Q1
Q0
Qm
Q0
Q1
BL=1
BL=2
BL=4
BL=8
BL=FP
Full Page counter rolls over
and continues to count.
m=255
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