參數(shù)資料
型號(hào): MH4S64CBMD-12B
廠商: Mitsubishi Electric Corporation
英文描述: 268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
中文描述: 268435456位(4194304字,64位)SynchronousDRAM
文件頁(yè)數(shù): 53/55頁(yè)
文件大?。?/td> 586K
代理商: MH4S64CBMD-12B
MH4S64BLG -7,-8,-10
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( 53
MITSUBISHI
ELECTRIC
29.Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0227-0.5
Serial Presence Detect Table II
31
32
Density of each bank on module
Command and Address signal input setup time
32MByte
2ns
N/A
08
20
00
36-61
62
Superset Information (may be used in future)
SPD Revision
option
rev 1.2A
00
12
rev 1
01
63
Checksum for bytes 0-62
Check sum for -8
Check sum for -10
44
41
64-71
72
Manufactures Jedec ID code per JEP-108E
Manufacturing location
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
1CFFFFFFFFFFFFFF
01
02
03
04
73-90
Manufactures Part Number
MH4S64BLG-8
MH4S64BLG-10
91-92
93-94
95-98
99-125
126
Revision Code
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
PCB revision
year/week code
serial number
option
100MHz
66MHz
rrrr
yyww
ssssssss
00
64
66
AF
AD
127
Intel specification CAS# Latency support
06
128+
Unused storage locations
open
00
-7,-8
-10
20
00
33
Command and Address signal input hold time
-7,-8
-10
1ns
N/A
10
00
34
Data signal input setup time
-7,-8
-10
2ns
N/A
1ns
N/A
35
Data signal input hold time
-7,-8
-10
10
00
-7,-8
-10
Check sum for -7
04
MH4S64BLG-7
4D4834533634424C472D3720202020202020
4D4834533634424C472D3820202020202020
-7,-8
-10
-7
-8
-10
4D4834533634424C472D3130202020202020
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