參數(shù)資料
型號: MH4V6445BXJJ-6
廠商: Mitsubishi Electric Corporation
英文描述: HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
中文描述: 超頁模式268435456位(4194304字,64位)動態(tài)隨機存儲器
文件頁數(shù): 7/26頁
文件大?。?/td> 152K
代理商: MH4V6445BXJJ-6
MH4V6445BXJJ-5,-6,-5S,-6S
HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
MITSUBISHI
ELECTRIC
( / 26 )
7
MITSUBISHI LSIs
Preliminary
Some of contents are subject
to change without notice.
MIT-DS-0233-0.0
24/Jul./1998
Read and Refresh Cycles
Limits
Parameter
Symbol
Unit
-6,-6S
Min
(Note 22)
(Note 22)
Write Cycle (Early Write and Delayed Write)
10000
10000
0
0
0
104
60
10
40
15
30
18
15
15
Max
Limits
Parameter
Symbol
Unit
(Note 24)
10000
10000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
10
0
104
60
10
40
15
10
0
10
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
Write cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Write setup time before /CAS low
Write hold time after /CAS low
/CAS hold time after /W low
/RAS hold time after /W low
Write pulse width
Data setup time before /CAS low or /W low
Data hold time after /CAS low or /W low
-6,-6S
Min
Max
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
Min
130
70
13
55
20
ns
ns
ns
ns
ns
ns
ns
ns
10000
10000
Max
10000
10000
13
13
13
0
ns
ns
ns
ns
ns
ns
ns
130
70
13
55
20
13
0
13
Min
ns
ns
ns
ns
ns
Max
tRC
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
tCAL
tOCH
tORH
Read cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read Setup time after /CAS high
Read hold time after /CAS low
Read hold time after /RAS low
Column address to /RAS hold time
Column address to /CAS hold time
/CAS hold time after /OE low
/RAS hold time after /OE low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
10
35
23
20
20
Read-Write and Read-Modify-Write Cycles
Limits
Parameter
Symbol
Unit
Min
133
89
Max
-6,-6S
(Note21)
(Note24)
(Note24)
(Note24)
Read write/read modify write cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read setup time before /CAS low
Delay time, /CAS low to /W low
Delay time, /RAS low to /W low
Delay time, address to /W low
/OE hold time after /W low
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS
tWCS(min) the cycle is an early write cycle
and the DQ pins will remain high impedance throughout the entire cycle. If tCWD
tCWD(min), tRWD
tRWD (min), tAWD
tAWD(min)
and tCPWD
tCPWD(min) (for Hyper page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the
data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until /CAS or /OE
goes back to VIH) is indeterminate.
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tOEH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10000
10000
44
0
32
77
47
15
44
82
Min
161
107
Max
-7,-7S
10000
10000
57
0
42
92
57
20
ns
57
99
ns
ns
ns
ns
ns
ns
-5,-5S
Min
10000
10000
0
0
0
84
50
8
35
13
25
13
13
13
Max
8
8
8
0
84
50
8
35
13
8
0
8
-5,-5S
Min
Max
10000
10000
Min
109
75 10000
10000
Max
-5,-5S
38
0
28
65
40
13
38
70
-7,-7S
ns
ns
ns
ns
-7,-7S
ns
ns
ns
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