參數(shù)資料
型號(hào)： MH64D64AKQH-75
廠商： Mitsubishi Electric Corporation
元件分類(lèi)： 圓形連接器
英文描述： Circular Connector; No. of Contacts:128; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:24; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:24-35 RoHS Compliant: No
中文描述： 4294967296位（67108864字64位），雙數(shù)據(jù)速率同步DRAM模塊
文件頁(yè)數(shù)： 18/40頁(yè)
文件大小： 362K
代理商： MH64D64AKQH-75
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0418-0.1
17.May.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
18
AC TIMING REQUIREMENTS
(Component Level)
(Ta=0 ~ 70°C , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
tCK
1.1
0.9
1.1
0.9
Read preamble
tRPRE
ns
tHP-1.0
tHP-
0.75
Output DQS valid window
tQH
ns
+0.6
+0.5
DQ Valid data delay time from DQS
tDQSQ
tCLmin
or
tCHmin
tCLmin
or
tCHmin
ns
15
10
15
10
CL=2
19
19
tCK
0.55
0.45
0.55
0.45
CLK Low level width
tCL
CLK cycle time
tCK
CL=2.5
16
15
14
14
AC Characteristics
-10
-75
0.6
0.4
0.6
0.4
1.1
0.9
1.1
0.9
0.25
0.25
0.6
0.4
0.6
0.4
0
0
15
15
0.2
0.2
0.2
0.2
0.35
0.35
0.35
0.35
1.25
0.75
1.25
0.75
+0.8
-0.8
+0.75
-0.75
+0.8
-0.8
+0.75
-0.75
2
1.75
tCK
ns
ns
tCK
tCK
ns
ns
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
0.6
0.5
0.6
0.5
15
8
15
7.5
tCK
0.45
0.55
0.45
+0.8
-0.8
+0.75
-0.75
+0.8
-0.8
+0.75
-0.75
Max.
Min.
Max.
Min.
Parameter
0.55
Read postamble
tRPST
tWPRE
Write preamble
tWPST
Write postamble
tWPRES
Write preamble setup time
Input Hold time (address and control)
tIH
tIS
Input Setup time (address and control)
tMRD
Mode Register Set command cycle time
tDSH
DQS falling edge hold time from CLK
tDSS
DQS falling edge to CLK setup time
tDQSL
DQS input Low level width
tDQSH
DQS input High level width
tDQSS
Write command to first DQS latching transition
tHP
Clock half period
Data-out-low impedance time from CLK//CLK
tLZ
tHZ
Data-out-high impedance time from CLK//CLK
tDIPW
DQ and DM input pulse width (for each input)
Input Hold time(DQ,DM)
Input Setup time (DQ,DM)
tDH
tDS
tCH
CLK High level width
ns
DQ Output Valid data delay time from CLK//CLK
tDQSCK
DQ Output Valid data delay time from CLK//CLK
ns
tAC
Notes
Unit
Symbol
相關(guān)PDF資料
PDF描述
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MH88422-1 Data Access Arrangement Preliminary Information
MH88422-2 Data Access Arrangement Preliminary Information
MH88422-3 Data Access Arrangement Preliminary Information
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