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參數(shù)資料
| 型號： | MH64D64AKQH-75 |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:128; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:24; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:24-35 RoHS Compliant: No |
| 中文描述： | 4294967296位（67108864字64位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 19/40頁 |
| 文件大?。?/td> | 362K |
| 代理商： | MH64D64AKQH-75 |
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0418-0.1
17.May.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
19
18
17
7.8
7.8
1
1
1
1
200
200
80
75
1
1
15
15
15
15
20
20
20
20
80
75
70
65
120,000
50
120,000
45
us
tCK
tCK
tCK
ns
tCK
ns
ns
ns
ns
ns
Average Periodic Refresh interval
tREFI
Exit Power down to -Read command
tXPRD
Exit Power down to command
tXPNR
tXSRD
Exit Self Ref. to -Read command
tXSNR
Exit Self Ref. to non-Read command
tWTR
Internal Write to Read Command Delay
ns
35
35
Auto Precharge write recovery + precharge time
tDAL
-10
-75
AC Characteristics
Max.
Min.
Max.
Min.
Parameter
tWR
Write Recovery time
tRRD
Act to Act Delay time
Row Precharge time
Row to Column Delay
tRP
tRCD
tRFC
Auto Ref. to Active/Auto Ref. command period
ns
Row Cycle time(operation)
tRC
Row Active time
ns
tRAS
Notes
Unit
Symbol
Output Load Condition
(for component measurement)
DQ
Output Timing
Measurement
Reference
Point
V
REF
V
REF
DQS
V
O U
V
REF
30pF
50ohm
V
TT
=V
REF
Zo=50 ohm
AC TIMING REQUIREMENTS(Continues)
(Ta=0 ~ 70°C , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MH88422BD-1 | Data Access Arrangement Preliminary Information |
| MH88422 | Line Interface Circuit Preliminary Information |
| MH88422-1 | Data Access Arrangement Preliminary Information |
| MH88422-2 | Data Access Arrangement Preliminary Information |
| MH88422-3 | Data Access Arrangement Preliminary Information |
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| MH64D72KLG-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLG-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
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