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參數(shù)資料
| 型號： | MH64D72KLG-75 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| 中文描述： | 4831838208位（67108864 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 10/38頁 |
| 文件大?。?/td> | 326K |
| 代理商： | MH64D72KLG-75 |
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH64D72KLG-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0389-1.1
20.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
10
FUNCTION TRUTH TABLE (continued)
Current State
/S0
/RAS /CAS
/WE
Address
Command
Action
RE-
FRESHING
H
X
X
X
X
DESEL
NOP (Idle after tRC)
L
H
H
H
X
NOP
NOP (Idle after tRC)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
MODE
REGISTER
SETTING
H
X
X
X
X
DESEL
NOP (Idle after tRSC)
L
H
H
H
X
NOP
NOP (Idle after tRSC)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE0 was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
Notes
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PDF描述 |
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| MH64D72KLH-10 | 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-75 | 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64S64APFH-6 | 4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH64D72KLH-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64FAD | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
| MH64FAD-R | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
| MH64FAG | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
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