參數(shù)資料
型號： MH64D72KLG-75
廠商： Mitsubishi Electric Corporation
英文描述： 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
中文描述： 4831838208位（67108864 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊
文件頁數(shù)： 17/38頁
文件大小： 326K
代理商： MH64D72KLG-75
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH64D72KLG-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0389-1.1
20.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
17
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70 , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
C
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70 C
868
382
454
3478
3730
2578
2740
2848
3100
1318
1480
868
940
940
688
760
2218
2380
2128
2290
-10
-75
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
power-down mode; CKE VIL (MAX); t CK = t CK MIN
mA
mA
mA
SELF REFRESH CURRENT: CKE 0.2V
AUTO REFRESH CURRENT: t RC = t RFC (MIN)
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
bank active; Address and control inputs changing once per clock
cycle; CL = 2.5; t CK = t CK MIN; DQ, DM and DQS inputs changing
twice per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One
bank active; Address and control inputs changing once per clock
cycle; CL = 2.5; t CK = t CK MIN; IOUT = 0 mA
ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN);
One bank; Active-Precharge; t RC = t RAS MAX; t CK = t CK MIN;
DQ,DM and DQS inputs changing twice per clock cycle; address and
other control inputs changing once per clock cycle
IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;
CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs
changing once per clock cycle
IDD2P
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; CKE VIL (MAX); t CK = t CK MIN
mA
OPERATING CURRENT: One Bank; Active-Read-Precharge;
Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0
mA;Address and control inputs changing once per clock cycle
OPERATING CURRENT: One Bank; Active-Precharge;
t RC = t RC MIN; t CK = t CK MIN; DQ, DM and DQS inputs changing
twice per clock cycle; address and control inputs changing once per
clock cycle
Parameter/Test Conditions
IDD4R
IDD3N
mA
mA
mA
mA
mA
mA
IDD6
IDD5
IDD4W
IDD3P
IDD2N
IDD1
IDD0
Notes
Unit
Limits(max)
Symbol
Symbol
Parameter/Test Conditions
Limits
Min.
Max.
Unit
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
High-Level Input Voltage (AC)
Low-Level Input Voltage (AC)
Input Differential Voltage, CLK and /CLK
Input Crossing Point Voltage, CLK and /CLK
Vref + 0.35
Vref - 0.35
V
V
V
V
μA
0.7
0.5*V
DD
Q-0.2
V
DD
Q + 0.6
IOZ
I
i
Off-state Output Current /Q floating Vo=0~V
DD
Q
Input Current / VIN=0 ~ VddQ
μA
-5
-10
5
10
0.5*V
DD
Q+0.2
Notes
7
8
9
O
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相關代理商/技術參數(shù)
參數(shù)描述
MH64D72KLH-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MH64D72KLH-75 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MH64FAD 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator
MH64FAD-R 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator
MH64FAG 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator
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