參數(shù)資料
型號: MH64S64APFH-6L
廠商: Mitsubishi Electric Corporation
英文描述: 4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM
中文描述: 4294967296位(67108864 -文字,64位)SynchronousDRAM
文件頁數(shù): 20/52頁
文件大?。?/td> 604K
代理商: MH64S64APFH-6L
MITSUBISHI LSIs
( 20
MITSUBISHI
ELECTRIC
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0392-0.1
MH64S64APFH-6,-6L,-7,-7L
4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM
16.Apr.2000
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read oparation can be interrupted by new read of the same or the other bank. Random
column access is allowed READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=2)
CK
Command
A10
DQ
READ
Ya
0
00
READ
Yb
0
00
Qa0
Qa2
Qb0
Qc0
Qa1
Qc1
Qc2
READ
Yc
0
10
Qc3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any active bank. Random column access
is allowed. In this case, the DQ should be controlled adequately by using the DQMB0-7 to
prevent the bus contention. The output is disabled automatically 2 cycle after WRITE
assertion.
Read Interrupted by Write (BL=4, CL=2)
CK
Command
A10
DQ
READ
Ya
0
00
Qa0
Write
Ya
0
00
Da0
Da1
Da2
Da3
DQMB0-7
A0-9,11-12
BA0,1
A0-9,11-12
BA0,1
ACT
Xa
Xa
00
Output disableby DQM
by WRITE
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MH64S64APFH-7 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM
MH64S64APFH-7L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM
MH64S72AWJA-6 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MH64S72AWJA-7 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MH64S72AWJA-8 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM