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參數(shù)資料
| 型號(hào)： | MH64S64APFH-6L |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM |
| 中文描述： | 4294967296位（67108864 -文字，64位）SynchronousDRAM |
| 文件頁數(shù)： | 4/52頁 |
| 文件大小： | 604K |
| 代理商： | MH64S64APFH-6L |
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MITSUBISHI LSIs
( 4
MITSUBISHI
ELECTRIC
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0392-0.1
MH64S64APFH-6,-6L,-7,-7L
4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM
16.Apr.2000
Serial Presence Detect Table I
Byte
0
1
2
3
4
5
6
7
8
9
Function described
SPD enrty data
128
256 Bytes
SDRAM
A0-A12
SPD DATA(hex)
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Voltage interface standard of this assembly
80
08
04
0D
A0-A9
2BANK
0A
02
x64
0
LVTTL
7.5ns
40
00
01
75
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
A0
54
10
SDRAM Access from Clock
tAC for CL=3
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
6ns
60
11
12
13
14
15
16
17
Non-PARITY
self refresh(7.8uS)
00
82
SDRAM width,Primary DRAM
Error Checking SDRAM data width
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported
x8
N/A
08
00
01
8F
1
1/2/4/8/Full page
# Banks on Each SDRAM device
4bank
04
18
CAS# Latency
19
20
21
22
CS# Latency
Write Latency
0
0
01
01
00
0E
SDRAM Module Attributes
SDRAM Device Attributes:General
non-buffered,non-registered
Precharge All,Auto precharge
23
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
24
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
25
26
SDRAM Cycle time(3rd highest CAS latency)
N/A
00
N/A
00
SDRAM Access form Clock(3rd highest CAS latency)
27
Precharge to Active Minimum
20ns
14
28
Row Active to Row Active Min.
15ns
20ns
0F
14
10ns
5.4ns
10ns
A0
6ns
60
29
RAS to CAS Delay Min
30
Active to Precharge Min
50ns
32
-7,-7L
-6,-6L
2/3
06
20ns
14
45ns
2D
-7,-7L
-6,-6L
-7,-7L
-6,-6L
-7,-7L
-7,-7L
-6,-6L
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MH64S64APFH-7 | 4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM |
| MH64S64APFH-7L | 4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM |
| MH64S72AWJA-6 | 4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH64S72AWJA-7 | 4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH64S72AWJA-8 | 4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH64S64APFH-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM |
| MH64S64APFH-7L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM |
| MH64S72AWJA-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH64S72AWJA-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH64S72AWJA-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
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