參數(shù)資料
型號(hào): MH8S64AQFC-8L
廠商: Mitsubishi Electric Corporation
英文描述: 536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
中文描述: 536870912位(8,388,608 -文字,64位)SynchronousDRAM
文件頁(yè)數(shù): 19/55頁(yè)
文件大小: 588K
代理商: MH8S64AQFC-8L
MH8S64PHC -7,-8,-10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
19
MITSUBISHI
ELECTRIC
9/ Dec. /1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0282-0.0
Multi Bank Interleaving READ (BL=4, CL=3)
CK
Command
A0-9
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
READ
Y
0
10
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
ACT
Xb
Xb
10
PRE
0
00
tRCD
/CAS latency
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CK
Command
A10
DQ
ACT
Xa
Xa
00
READ
Y
1
00
Qa0
Qa1
Qa2
Qa3
ACT
Xa
Xa
00
Internal precharge begins
tRCD
tRP
READ Auto-Precharge Timing (BL=4)
CK
Command
ACT
READ
Internal Precharge Start Timing
DQ
Qa0
Qa1
Qa2
Qa3
DQ
Qa0
Qa1
Qa2
Qa3
CL=3
CL=2
A0-9
BA0,1
A11
Xa
Xb
A11
Xa
Xa
BL
BL + tRP
BL
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