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參數(shù)資料
| 型號(hào)： | MH8S64BBKG-7L |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| 中文描述： | 536870912位（8388608 -文字，64位）SynchronousDRAM |
| 文件頁數(shù)： | 4/55頁 |
| 文件大?。?/td> | 588K |
| 代理商： | MH8S64BBKG-7L |
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MH8S64PHC -7,-8,-10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( 4
MITSUBISHI
ELECTRIC
9/ Dec. /1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0282-0.0
Serial Presence Detect Table I
Byte
0
1
2
3
4
5
6
7
8
9
Function described
SPD enrty data
128
256 Bytes
SDRAM
A0-A11
A0-A8
1BANK
x64
0
LVTTL
SPD DATA(hex)
80
08
04
0C
09
01
40
00
01
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
A0
Cycle time for CL=3
10
SDRAM Access from Clock
tAC for CL=3
6ns
8ns
60
80
11
12
13
14
15
16
17
18
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
SDRAM width,Primary DRAM
Error Checking SDRAM data width
Non-PARITY
self refresh(15.625uS)
x16
N/A
1
1/2/4/8/Full page
4bank
2/3
00
80
10
00
01
8F
04
06
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported
# Banks on Each SDRAM device
CAS# Latency
19
20
21
22
23
CS# Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes:General
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
0
0
01
01
00
0E
A0
non-buffered,non-registered
Precharge All,Auto precharge
10ns
13ns
15ns
D0
F0
24
SDRAM Access form Clock(2nd highest CAS latency)
7ns
8ns
N/A
N/A
20ns
30ns
70
80
00
00
14
1E
tAC for CL=2
25
26
27
SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
Precharge to Active Minimum
28
Row Active to Row Active Min.
20ns
14
-7,-8
-10
10ns
-8
-8
-10
-7,-8
-7
6ns
60
-7
29
RAS to CAS Delay Min
20ns
30ns
14
1E
-7,-8
30
Active to Precharge Min
50ns
32
60ns
3C
-7,-8
-10
-7,-8,-10
-10
-10
-7,-8,-10
-10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MH8S64BBKG-8 | 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64BBKG-8L | 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64DALD-6 | 536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM |
| MH8S64DALD-7 | 536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM |
| MH8S64DALD-8 | 536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH8S64BBKG-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64BBKG-8L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64BMG-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64BMG-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64BMG-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
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