參數(shù)資料
型號： MH8S64DALD-7
廠商： Mitsubishi Electric Corporation
英文描述： 536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
中文描述： 536870912位（8388608 -文字，64位）同步DRAM
文件頁數(shù)： 23/55頁
文件大?。?/td> 588K
代理商： MH8S64DALD-7
MH8S64PHC -7,-8,-10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
23
MITSUBISHI
ELECTRIC
9/ Dec. /1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0282-0.0
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same or the other bank. Read
to PRE interval is minimum 1 CK. A PRE command output disable latency is equivalent to
the /CAS Latency.As a result, READ to PRE interval determines valid data length to be
output.The figure below shows examples of BL=4.
Read Interrupted by Precharge (BL=4)
CK
Command
DQ
READ
PRE
Q0
Q1
Command
DQ
READ
PRE
Q0
Q1
Command
DQ
READ
PRE
Q0
Q2
Q1
Command
DQ
READ
PRE
Q0
Q1
Q2
CL=3
CL=2
Command
DQ
READ PRE
Q0
Command
DQ
READ PRE
Q0
相關(guān)PDF資料
PDF描述
MH8S64DALD-8 536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
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MH8S64DBKG-6L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MH8S64DBKG-7 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MH8S64DALD-8 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
MH8S64DBKG-6 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MH8S64DBKG-6L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MH8S64DBKG-7 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MH8S64DBKG-7L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
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