- 您現在的位置：買賣IC網 > PDF目錄371108 > MH8S64DBKG-6L (Mitsubishi Electric Corporation) 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM PDF資料下載
參數資料
| 型號： | MH8S64DBKG-6L |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| 中文描述： | 536870912位（8388608 -文字，64位）SynchronousDRAM |
| 文件頁數： | 20/55頁 |
| 文件大?。?/td> | 588K |
| 代理商： | MH8S64DBKG-6L |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁
MH8S64PHC -7,-8,-10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
20
MITSUBISHI
ELECTRIC
9/ Dec. /1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0282-0.0
Multi Bank Interleaving WRITE (BL=4)
CK
Command
A10
DQ
ACT
Xa
Xa
00
Write
Y
0
00
Write
Y
0
10
Da0
Da1
Da2
Da3
ACT
Xb
Xb
10
PRE
0
00
tRCD
Db0
Db1
Db2
Db3
tRCD
CK
Command
A10
DQ
ACT
Xa
Xa
00
Write
Y
1
00
Da0
Da1
Da2
Da3
ACT
Xa
Xa
00
Internal precharge begins
tRCD
tRP
WRITE with Auto-Precharge (BL=4)
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set
at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the
Burst Length is BL. The start address is specified by A8-0, and the address sequence of burst
data is defined by the Burst Type. A WRITE command may be applied to any active bank, so
the row precharge time(tRP) can be hidden behind continuous input data by interleaving the
multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is
required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is
performed. Any command(READ, WRITE, PRE, ACT) to the same bank is inhibited till the
internal precharge is complete. The internal precharge begins at tWR after the last input data
cycle. The next ACT command can be issued after tRP from the internal precharge timing.
The Mode Register can be WRITE command is issued and the remaining burst length is
ignored.The read data burst length os unaffected while in this mode.
A0-9
BA0,1
A0-9
BA0,1
A11
Xa
Xb
0
PRE
0
10
0
A11
Xa
Xa
tWR
相關PDF資料 |
PDF描述 |
|---|---|
| MH8S64DBKG-7 | 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64DBKG-7L | 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64DBKG-8 | 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64DBKG-8L | 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S72BAFD-8 | LJT 37C 37#22D PIN WALL RECP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MH8S64DBKG-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64DBKG-7L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64DBKG-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64DBKG-8L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
| MH8S64FFC-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。