參數(shù)資料
型號: MH8S64DBKG-6L
廠商: Mitsubishi Electric Corporation
英文描述: 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
中文描述: 536870912位(8388608 -文字,64位)SynchronousDRAM
文件頁數(shù): 33/55頁
文件大?。?/td> 588K
代理商: MH8S64DBKG-6L
MH8S64PHC -7,-8,-10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
33
MITSUBISHI
ELECTRIC
9/ Dec. /1998
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0282-0.0
AC TIMING REQUIREMENTS
(SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
CK
Signal
1.4V
1.4V
Any AC timing is
referenced to the input
signal crossing through
1.4V.
Limits
-8
Min.
Symbol Parameter
-7
Unit
Min.
Max.
tCLK
CK cycle time
ns
ns
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tSRX
tPDE
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Mode Register Set Cycle time
Self Refresh Exit time
Power Down Exit time
3
3
1
2
1
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
70
20
50
20
20
20
20
10
10
100K
tREF
Refresh Interval time
64
ms
Max.
3
3
1
2
1
13
10
10
70
20
50
20
20
20
20
10
10
100K
64
CL=2
CL=3
-10
Min.
Max.
4
4
1
3
1
15
10
10
90
30
60
30
15
20
20
10
10
100K
64
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