參數(shù)資料
型號: MH8S72DALD-8
廠商: Mitsubishi Electric Corporation
英文描述: 603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
中文描述: 603979776位(8388608 - Word的72位)同步DRAM
文件頁數(shù): 14/56頁
文件大小: 732K
代理商: MH8S72DALD-8
MITSUBISHI
ELECTRIC
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MH8S72BAFD -7, -8
MITSUBISHI LSIs
POWER ON SEQUENCE
Preliminary
Spec.
1/ Dec./1998
MIT-DS-0273-0.2
14
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB high and NOP
condition at the inputs.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500μs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which may
be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is
ready for new command.
R:Reserved for Future Use
FP: Full Page
/S
/RAS
/CAS
/WE
BA0,1 A11-0
CK
V
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BURST
LENGTH
BT= 0
1
2
4
8
R
R
R
FP
BT= 1
1
2
4
8
R
R
R
R
0
1
BURST
TYPE
SEQUENTIAL
INTERLEAVED
A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA1
BA0
0
0
WM
0
0
LTMODE
BT
BL
0
0
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
LATENCY
MODE
/CAS LATENCY
2
3
R
R
R
R
R
R
0
1
WRITE
MODE
BURST
SINGLE BIT
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