參數(shù)資料
型號： MIC5191
廠商： Micrel Semiconductor,Inc.
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Ultra High-Speed, High-Current Active Filter/LDO Controller
中文描述： 超高速，高電流有源濾波器/ LDO控制器
文件頁數(shù)： 7/13頁
文件大?。?/td> 182K
代理商： MIC5191
A
pril
200
4
7
M
9999-
0
4
2
8
0
4
MIC51
9
1
Applications Information
Designing with the MIC5191
Anatomy of a transient response
A
voltage
regulator
can
maintain
a
set
output
voltage
while
its
exterior
world
is
pushing
and
pulling
in
its
demand
for
power
.
T
he
measure
of
a
regulator
is
generally
how
accurately
and
effectively
it
can
maintain
that
voltage,
regardless
of
how
the
load
demands
power
. O
ne
measure
of
regulator
response
is
the
load
step
. T
his
is
an
intuitive
loo
k
at
how
the
regulator
responds
to
a
change
in
load
current
. F
igure
2
is
a
loo
k
at
the
transient
response
to
a
load
step
.
M
icrel
Figure 2. Typical Transient Response
A
t
the
start
of
a
circuit's
power
demand,
the
output
voltage
is
regulated
to
its
set
point,
while
the
load
current
runs
at
a
constant
rate
. F
or
many
different
reasons,
a
load
may
as
k
for
more
current
without
warning
.
When
this
happens,
the
regu-
lator
needs
some
time
to
determine
the
output
voltage
drop
.
T
his
is
determined
by
the
speed
of
the
control
loop
. S
o,
until
enough
time
has
elapsed,
the
control
loop
is
oblivious
to
the
voltage
change
. T
he
output
capacitor
must
bear
the
burden
of
maintaining
the
output
voltage
.
V
Ldi
dt
=
S
ince
this
is
a
sudden
change
in
voltage,
the
capacitor
will
try
to
maintain
voltage
by
discharging
current
to
the
output
. T
he
first
voltage
drop
is
due
to
the
output
capacitor's
ES
L
(equiva-
lent
series
inductance)
. T
he
ES
L
will
resist
a
sudden
change
in
current
from
the
capacitor
and
drop
the
voltage
quic
k
ly
. T
he
amount
of
voltage
drop
during
this
time
will
be
proportional
to
the
output
capacitor's
ES
L
and
the
speed
at
which
the
load
steps
. S
lower
load
current
transients
will
reduce
this
effect
.
V
L
di
dt
↓=
↑
P
lacing
multiple
small
capacitors
with
low
ES
L
in
parallel
can
help
reduce
the
total
ES
L
and
reduce
voltage
droop
during
high
speed
transients
. F
or
high
speed
transients,
the
greatest
voltage
deviation
will
generally
be
caused
by
output
capacitor
ES
L
and
parasitic
inductance
.
V
L
di
dt
↓=
↓
A
fter
the
current
has
overcome
the
effects
of
the
ES
L,
the
output
voltage
will
begin
to
drop
proportionally
to
time
and
inversely
proportional
to
output
capacitance
.
T
he
relationship
to
output
voltage
variation
will
depend
on
two
aspects,
loop
bandwidth
and
output
capacitance
. T
he
output
capacitance
will
determine
how
far
the
voltage
will
fall
over
a
given
time
.
With
more
capacitance,
the
drop
in
voltage
will
fall
at
a
decreased
rate
. T
his
is
the
reason
that
for
the
same
bandwidth,
more
capacitance
provides
a
better
transien-
response
1
A
lso,
the
time
it
ta
k
es
for
the
regulator
to
respond
is
directl
proportional
to
its
gain
bandwidth
.
Higher
bandwidth
contro
loops
respond
quic
k
er
causing
a
reduced
droop
on
the
suppl
for
the
same
amount
of
capacitance
F
inal
recovery
bac
k
to
the
regulated
voltage
is
the
final
phas
of
transient
response
and
the
most
important
factors
are
gai
and
time
.
Higher
gain
at
higher
frequency
will
get
the
outpu
voltage
closer
to
its
regulation
point
quic
k
er
. T
he
final
settlin
point
will
be
determined
by
the
load
regulation,
which
i
proportional
to
DC
(
0
Hz)
gain
and
the
associated
loss
terms
T
here
are
other
factors
that
contribute
to
large
signal
tran-
sient
response,
such
as
source
impedance,
phase
margin
and
PSRR. F
or
example,
if
the
input
voltage
drops
due
t
source
impedance
during
a
load
transient,
this
will
contribut
to
the
output
voltage
deviation
by
filtering
through
to
th
output
reduced
by
the
loops
PSRR
at
the
frequency
of
th
voltage
transient
. I
t
is
straightforward:
good
input
capaci-
tance
reduces
the
source
impedance
at
high
frequencies
Having
between
35
°
and
4
5
°
of
phase
margin
will
help
spee
up
the
recovery
time
. T
his
is
caused
by
the
initial
overshoo
in
response
to
the
loop
sensing
a
low
voltage
Compensatio
T
he
MIC51
9
1
allows
the
flexibility
of
externally
controlling
th
gain
and
bandwidth
. T
his
allows
the
MIC51
9
1
design
to
b
tailored
to
each
individual
design
I
n
designing
the
MIC51
9
1
,
it
is
important
to
maintain
ad-
equate
phase
margin
. T
his
is
generally
achieved
by
havin
the
gain
cross
the
0
d
B
point
with
a
single
pole
20
d
B
/decad
roll-off
. T
he
compensation
pin
is
configured
as
F
igure
demonstrates
Figure 3. Internal Compensatio
V
C
idt
=
∫
1
V
C
idt
↓=
↑
∫
V
C
idt
↓=
∫
↓
1
T
ime
∫
idt
C
V =
1
BW
1
L
u
O
u
o
A
-
C
o
O
utput
voltage
vs
.
time
during
recovery
is
directly
proportional
to
gain
vs
.
frequency
.
V
=
L
di
dt
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