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參數(shù)資料
| 型號： | MIC74YQS TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C 8B 16QSOP |
| 標準包裝： | 2,500 |
| 接口： | I²C，SM 總線 |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 是 |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MIC74YQSTR MIC74YQSTR-ND |
Micrel, Inc.
MIC74
October 2006
7
M9999-101006
Functional Diagram
GND
VDD
Pn (typical I/O port)
S
Q
QR
EDGE
DETECT
INTn
IMn
STATUSn
STATUS_READn
DATAn
(INPUT)
OUT_CFGn
DIRn
DATAn
(OUTPUT)
Typical I/O Port (Fan Speed Control Logic Not Shown)
Functional Description
Pin Descriptions
VDD
Power supply input connection. See “Operating Ratings.”
GND
Ground or return connection for all MIC74 functions.
CLK
An CLK signal is provided by the host (master) and is
common to all devices on the bus. The CLK signal
controls all transactions in both directions on the bus and
is applied to each MIC74 at the CLK pin.
DATA
Serial data is bidirectional and is common to all devices
on the bus. The MIC74’s DATA output is open-drain.
The DATA line requires one external pull-up resistor or
current source per system that can be located anywhere
along the line.
A2, A1, A0
An MIC74 responds to its own unique address which is
assigned using the A0–A2 pins. A0–A2 set the three
LSBs (least significant bits) of the MIC74’s 7-bit slave
address. The three address pins allow eight unique
MIC74 addresses in a system. When the MIC74’s
address matches an address received in the serial bit
stream, communication is initiated.
A2, A1 and A0 should be connected to GND or VDD.
The state of these pins is sampled only once at device
power-on. New slave addresses are not accepted unless
the MIC74 is powered off then on.
Inputs
MIC74 Slave Address
A2
A1
A0
Bianary
Hex
0
010 0000b
20h
0
1
010 0001b
21h
0
1
0
010 0010b
22h
0
1
010 0011b
23h
1
0
010 0100b
24h
1
0
1
010 0101b
25h
1
0
010 0110b
26h
1
010 0111b
27h
Table 1. MIC74 Address Configuration
Alert Response Address
The MIC74 also responds to the ARA (Alert Response
Address). The ARA is used by the master (host) to
request the address of a slave that has provided an
interrupt to the master via the /ALERT line.
The ARA is a single address (0001 100) common to all
slaves and is described in more detail under “Interrupt
Generation” with related information under “/ALERT.”
Also see Figure 7.
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