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參數(shù)資料
| 型號(hào)： | MIC74YQS TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 18/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C 8B 16QSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 接口： | I²C，SM 總線 |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 是 |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MIC74YQSTR MIC74YQSTR-ND |
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Micrel, Inc.
MIC74
October 2006
9
M9999-101006
Address
Power-On Default
Register
Name
Register
Description
Binary
Hex
Available
Operations
Binary
Hex
DEV_CONFIG
Device Configuration
0000 0000b
00h
8-bit read/write
0000 0000b
00h
DIR
I/O Direction
0000 0001b
01h
8-bit read/write
0000 0000b
00h
OUT_CFG
Output Configuration
0000 0010b
02h
8-bit read/write
0000 0000b
00h
STATUS
Interrupt Status
0000 0011b
03h
8-bit read
0000 0000b
00h
INT_MASK
Interrupt Mask
0000 0100b
04h
8-bit read/write
0000 0000b
00h
DATA
General-Purpose I/O
0000 0101b
05h
8-bit read/write
1111 1111b
FFh
FAN_SPEED
Fan Speed
0000 0110b
06h
8-bit read/write
0000 0000b
00h
Table 2. Register Summary
Fan Start-Up
Any time the fan speed register contains zero (fan is off)
and then a nonzero value is written to FAN_SPEED, the
/FS[2:0] and /SHDN outputs will assume the highest fan
speed state for approximately one second (tSTART).
Following this interval, the state of the fan speed control
outputs will assume the value indicated by the contents
of FAN_SPEED. This insures that the fan will start
reliably when low speed operation is desired. The tSTART
interval is generated by an internal oscillator and
counters. At the end of tSTART, this oscillator is powered
down to reduce overall power consumption.
MIC74
VIN
/SHDN
GND
VOUT
FB
RF2
RPULL-UP
/FS2
RF2
/FS1
RF2
RMIN_SPEED
/FS0
/SHDN
FAN
RFB
Regulator
Figure 1. Fan Speed Control Application
Proper sequencing of the /FS[2:0] and /SHDN signals is
performed by the MIC74’s internal logic state machine.
When activating the fan from the off state, the /FS[2:0]
lines change state first, then, after a delay equal to one-
half of tSTART, the /SHDN pin is deasserted. Conversely,
when the fan is shutdown (zero is written to
FAN_SPEED), the /SHDN pin is deasserted first. The
/FS[2:0] lines are subsequently deasserted after a delay
of 12tSTART. The internal oscillator is also powered down
following the tSTART/2 interval at fan shut-down. These
timing relationships are illustrated in Figure 2.
Interrupt Generation
Assuming that any or all of the I/O’s are configured as
inputs, the MIC74 will reflect the occurrence of an input
change in the corresponding bit in the status register,
STATUS. This action cannot be masked. An input
change will only generate an interrupt to the host if
interrupts are properly configured and enabled.
The MIC74 can operate in either polled mode or interrupt
mode. In the case of polled operation, the host
periodically reads the contents of STATUS to determine
the device state. The act of reading STATUS clears its
contents. Repeating events which have occurred since
the last read from STATUS will not be discernable to the
host.
Interrupts are only generated if the global interrupt
enable bit, IE, in the DEV_CFG register is set. The
/ALERT signal will be asserted (driven low) when an
interrupt is generated. The MIC74 expects to be
interrogated using the ARA when it has generated an
interrupt output. Once it has successfully responded to
the ARA (Alert Response Address), the /ALERT output
will be deasserted. The contents of the status register
will not be cleared until it is read using a read byte
operation.
If a given system does not wish to use the SMBus ARA
protocol for reporting interrupts, the system may simply
poll the contents of the status register after detecting an
interrupt on /ALERT. This action will clear the contents of
STATUS and cause /ALERT to be deasserted. Reading
the status register is an acceptable substitute for using
the ARA protocol. Presumably, however, it will involve
higher system overhead since all the devices on the bus
must be polled to determine which one generated the
interrupt.
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