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參數(shù)資料
| 型號： | MIP7365-450B1M |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 450 MHz, MICROPROCESSOR, PBGA256 |
| 封裝： | 26 X 26 MM, TBGA-256 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 285K |
| 代理商： | MIP7365-450B1M |
6
SCD7365 Rev B 1/11/07
Aeroflex Plainview
Initialization Interface
PIN NAME
TYPE
DESCRIPTION
BigEndian
Input
Big Endian / Little Endian Control
Allows the system to change the processor addressing
VccOK
Input
Vcc is OK
When asserted, this signal indicates to the MIP7365 that the VccInt power supply has been
above the recommended value for more than 100 milliseconds and will remain stable. The
assertion of VccOK initiates the reading of the boot-time mode control serial stream.
ColdReset*
Input
Cold Reset
This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted
synchronously with SysClock.
Reset*
Input
Reset
This signal must be asserted for any reset sequence. It may be asserted synchronously or
asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset must be
de-asserted synchronously with SysClock.
ModeClock
Output
Boot Mode Clock
Serial boot-mode data clock output at the system clock frequency divided by two hundred and
fifty six.
Modein
Input
Boot Mode Data In
Serial boot-mode data input.
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