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參數資料
| 型號： | MJ-80C32E-30-E |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Rad. Tolerant 8-bit ROMless Microcontroller |
| 中文描述： | 8-BIT, 30 MHz, MICROCONTROLLER, QCC44 |
| 封裝： | QFP-44 |
| 文件頁數： | 10/20頁 |
| 文件大?。?/td> | 298K |
| 代理商： | MJ-80C32E-30-E |
10
80C32E
4149M–AERO–06/04
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
6. Operating I
CC
is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
= 5 ns, V
IL
= V
SS
+ 0.5V,
V
IH
= V
CC
- 0.5V; XTAL2 N.C.; EA = Port 0 = V
CC
; RST = V
SS
. The internal ROM runs the code 80 FE (label: SJMP label). I
CC
would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is
the worst case.
Figure 2.
I
CC
Test Condition, Under Reset
Figure 3.
Operating I
CC
Test Condition
Figure 4.
I
CC
Test Condition, Idle Mode
EA
V
CC
V
CC
I
CC
(NC)
CLOCK
SIGNAL
V
CC
All other pins are disconnected.
RST
XTAL2
XTAL1
V
SS
V
CC
P0
EA
V
CC
V
CC
I
CC
(NC)
CLOCK
SIGNAL
All other pins are disconnected.
RST
XTAL2
XTAL1
V
SS
V
CC
P0
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
EA
XTAL2
XTAL1
V
SS
V
CC
V
CC
I
CC
(NC)
P0
V
CC
All other pins are disconnected.
CLOCK
SIGNAL
Reset = Vss after a high pulse
during at least 24 clock cycles
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