- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359167 > MK2042-01SITR Communications Clock Monitor PDF資料下載
參數(shù)資料
| 型號(hào)： | MK2042-01SITR |
| 英文描述： | Communications Clock Monitor |
| 中文描述： | 通信時(shí)鐘監(jiān)視器 |
| 文件頁(yè)數(shù)： | 2/6頁(yè) |
| 文件大?。?/td> | 81K |
| 代理商： | MK2042-01SITR |
MK2042-01
Communications Clock Monitor
MDS 2042-01
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
2
Revision 102600
Printed 11/15/00
ICRO
C
LOC K
ADVANCE INFORMATION
Pin Descriptions
Type: I = Input, O = output, P = power supply connection
All inputs have an internal pull-up.
Pin Assignment
16 pin (150 mil) SOIC
1
2
3
4
5
6
7
8
12
11
10
9
INB
INA
GND
SELB
REFIN
S1
S2
LOW
GND
NO_INA
HIGH
S0
OE
VDD
CENTER
14
13
15
16
CLKOUT
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
S0
S1
S2
INB
INA
GND
SELB
REFIN
CENTER
GND
LOW
HIGH
NO_INA
CLKOUT
VDD
OE
Type Description
I
Clock Count Select 0. Determines allowed number of missing clock edges per table above.
I
Clock Count Select 1. Determines allowed number of missing clock edges per table above.
I
Clock Count Select 2. Determines allowed number of missing clock edges per table above.
I
Input Clock B.
I
Input Clock A.
P
Connect to ground.
I
Mux select. Selects INB when high.
I
Reference Clock Input.
I
Enables HIGH and LOW pins when high.
P
Connect to ground.
O
Sets low end of centering range.
O
Sets high end of centering range.
O
Goes high when clock on INA stops.
O
Clock output.
P
Connect to +3.3 V or +5 V.
I
Output Enable. Tri-states CLKOUT when low.
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Nominal Count
34
18
130
66
10
6
2
2
Clock Loss Detector Settings
Due to the possible phase differences between
the REFIN clock and the INA clock, the
Nominal Count has a tolerance of -0/+1
REFIN clock edges.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-34SITR | 3.3 V Communications Clock PLL |
| MK2049-35SITR | 3.3 V Communications Clock PLL |
| MK2049-36SITR | 3.3 V Communications Clock PLL |
| MK2058-01SITR | Communications Clock Jitter Attenuator |
| MK2304S-2 | ZERO DELAY, LOW SKEW BUFFER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-01 | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLL |
| MK2049-01S | 制造商:Integrated Device Technology Inc 功能描述:IC SM CLK GEN T1/E1/T3/E3 PLL 8KHZ P-SO- - Bulk |
| MK2049-01SI | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLL |
| MK2049-01SITR | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLL |
| MK2049-01STR | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK SYNTHESIZER SGL 20SOIC - Tape and Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。