- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69033 > MK2049-10SILF 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 PDF資料下載
參數(shù)資料
| 型號： | MK2049-10SILF |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大小： | 185K |
| 代理商： | MK2049-10SILF |
Communications Clock PLL
MDS 2049-10 E
5
Revision 021402
Integrated Circuit Systems, Inc. q 525 Race Street San Jose, CA 95126 q tel (408) 295-9800 q
www.icst.com
MK2049-10
(see also notes below regarding C2) which may be
required for network clock wander transfer compliance.
A high damping factor may also increase output clock
jitter when there is excess digital noise in the system
application, due to the reduced ability of the PLL to
respond to and therefore compensate for phase noise
ingress.
Notes on setting the value of C2
As another general rule, the following relationship
should be maintained between components C1 and C2
in the loop filter:
C2 establishes a second pole in the VCXO PLL loop
filter. For higher damping factors (> 1), calculate the
value of C2 based on a C1 value that would be used for
a damping factor of 1. This will prevent excessive
baseband peaking and loop instability that can lead to
output jitter.
C2 also dampens VCXO input voltage modulation by
the charge pump correction pulses. A C2 value that is
too low will result in increased output phase noise at
the phase detector frequency due to this. In extreme
cases where input jitter is high, charge pump current is
high, and C2 is too small, the VCXO input voltage can
hit the supply or ground rail resulting in non-linear loop
response.
The best way to set the value of C2 is to use the filter
response software available from ICS (please refer to
the following section). C2 should be increased in value
until it just starts affecting the passband peak.
Loop Filter Response Software
ICS has a PC-based program available that simulates
VCXO PLL loop response characteristics. This can be
used instead of the above bandwidth and damping
factor equations. The user enters external loop filter
component values and other listed device
characteristics. The program generates a PLL
frequency response graph, which translates to jitter
attenuation characteristics. Normalized bandwidth
(NBW) and damping factor values are also calculated.
To obtain this free software please contact the
applications department of ICS, MicroClock Division, at
(408) 297-1201.
VCXO Gain (KO) vs. XTAL Frequency
C
2
C
1
20
------
=
10
20
15
25
30
2000
3000
4000
5000
6000
1000
C rystal Frequ en cy, M H z
V
C
X
O
G
a
in
(
K
O
),
H
z
p
e
r
V
o
lt
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-10SITR | 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-10SITRLF | 44.736 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2058-01SILF | 27 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2058-01SILFTR | 27 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2058-01SITR | OTHER CLOCK GENERATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-34 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-34A | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 Volt Communications Clock VCXO PLL |
| MK2049-34SAI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2049-34SAILF | 功能描述:時鐘合成器/抖動清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK2049-34SAILFTR | 功能描述:時鐘合成器/抖動清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。