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參數(shù)資料
| 型號： | MK2069-02GITR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 210K |
| 代理商： | MK2069-02GITR |
MK2069-02
VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR
6
MK2069-02
REV G 050203
Setting the VCXO PLL Loop Response.
The VCXO PLL loop response is determined both by fixed
device characteristics and by other characteristics set by the
user. This includes the values of RS, CS, CP and RSET as
shown in the External VCXO PLL Components figure on this
page.
The VCXO PLL loop bandwidth is approximated by:
Where:
RS = Value of resistor RS in loop filter in Ohms
ICP = Charge pump current in amps
(see table on page 8)
KO = VCXO Gain in Hz/V
(see table on page 8)
PV = PV Divider value = 2 to 4097
FV = FV Divider value= 1 to 4096
SV = SV Divider value= 1,2,4,6,8,10,12 or 16
The above equation calculates the “normalized” loop
bandwidth (denoted as “NBW”) which is approximately
equal to the - 3dB bandwidth. NBW does not take into
account the effects of damping factor or the second pole
imposed by CP. It does, however, provide a useful
approximation of filter performance.
To prevent jitter on VCLK due to modulation of the VCXO
PLL by the phase detector frequency, the following general
rule should be observed:
.
The PLL loop damping factor is determined by:
Where:
CS = Value of capacitor CS in loop filter in Farads
The above equations illustrate that the VCXO PLL
bandwidth and damping factor, together, can be increased
or decreased by changing only the value of the PV Divider.
The frequency multiplication ratio is not changed. This is a
feature unique to the MK2069-02.
External VCXO PLL Components
In general, the loop damping factor should be 0.7 or greater
to ensure output stability. A higher damping factor will create
less peaking in the passband and will further assure output
stability with the presence of system and power supply
noise. A damping factor of 4 will ensure a passband peak
less then 0.2dB which may be required for network clock
wander transfer compliance. A higher damping factor may
NBW(VCXO PLL)
R
S
I
CP
×
K
O
×
2
π PV
×
FV
SV
×
--------------------------------------------------
=
NBW(VCXO PLL)
f(Phase Detector)
20
---------------------------------------
≤
DF(VCLK)
R
S
2
------
I
CP
C
S
×
K
O
×
PV
FV
×
SV
×
-------------------------------------
×
=
R
SET
C
P
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X1
15
16
X2
17
18
LFR
19
LF
20
ISET
25
26
27
28
36
35
34
33
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
32
31
30
29
M
K
2069
XTAL
C
L
C
L
R
S
C
S
Optional
Crystal Tuning
Capacitors
DON'T STUFF
Refer to "Crystal Tuning Load
Capacitors" Section
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MK2069-03 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Clock Translator with High Multiplication |
| MK2069-03GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC 包裝:管件 |
| MK2069-03GITR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2069-04 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Universal Clock Translator |
| MK2069-04GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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