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參數(shù)資料
| 型號： | MK2762-01SLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 33.333 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 24K |
| 代理商： | MK2762-01SLF |
MK2762
MPEG/Set-Top Clock Source
MDS2762B
2
Revision 5307
Printed 7/25/97
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Pin Descriptions
Audio Clock Decoding Table (in MHz)
Key: I = Input, O = output, P = power supply connection
Pin Assignment
Number
Name
Type
Description
1
AS1
I
Audio clock Select 1. Selects audio clocks on pins 6 and 8 per table above.
2
X2
O
Crystal connection. Connect to 27 MHz crystal. Leave unconnected for clock input.
3
X1/ICLK
I
Crystal connection. Connect to 27 MHz crystal or connect to 27 MHz input clock.
4
VDD
P
Connect to +5V.
5
GND
P
Connect to ground.
6
ACLK/2
O
Audio Clock output divided by 2. Determined by status of AS1, AS0. See table above.
7
33.3M
O
33.3333 MHz clock output.
8
ACLK
O
Audio Clock output. Determined by status of AS1, AS0. See table above.
9
13.5M
O
13.50 MHz clock output.
10
27M
O
Inverted 27.00 MHz clock output.
11
27M
O
27.00 MHz low-skew clock output.
12
GND
P
Connect to ground.
13
VDD
P
Connect to +5V.
14
27M
O
27.00 MHz low-skew clock output.
15
27M
O
27.00 MHz low-skew clock output.
16
AS0
I
Audio clock Select 0. Selects audio clocks on pins 6 and 8 per table above.
MK2762
1
16
2
3
4
15
14
13
VDD
GND
X2
VDD
27M
16 pin (150 mil) SOIC
5
6
7
8
12
11
10
9
13.5M
27M
X1/ICLK
27M
AS1
AS0
27M
ACLK/2
GND
ACLK
33.3M
0 = connect directly to ground
1 = connect directly to VDD
AS1
AS0
ACLK
ACLK/2
Pin 1 Pin 16
Pin 8
Pin 6
0
8.192
4.096
0
1
11.2896
5.6448
1
0
12.288
6.144
1
24.576
12.288
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