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參數(shù)資料
| 型號(hào)： | MK2762-01SLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 33.333 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 24K |
| 代理商： | MK2762-01SLF |
MK2762
MPEG/Set-Top Clock Source
MDS2762B
3
Revision 5307
Printed 7/25/97
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 20 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 5.0V unless noted)
Operating Voltage, VDD
4.5
5.5
V
Input High Voltage, VIH, X1/ICLK pin only
3.5
2.5
V
Input Low Voltage, VIL, X1/ICLK pin only
2.5
1.5
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD
No Load
37
mA
Short Circuit Current
Each output
±100
mA
Input Capacitance
7
pF
Frequency error
note 2
0
ppm
AC CHARACTERISTICS (VDD = 5.0V unless noted)
Input Frequency
27.000
MHz
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At VDD/2
45
50
55
%
Absolute Jitter, short term
Variation from mean
200
ps
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With 27.000 MHz input clock.
External Components
The MK2762 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1F should be connected between VDD and GND, as close to the MK2762 as possible. A
series termination resistor of 33
may be used for each clock output. If a clock input is not used, the
27.00 MHz crystal must be connected as close to the chip as possible. The crystal should be a fundamental
mode, parallel resonant, 50 ppm or better. On-chip capacitors eliminate the need for external crystal caps
when a crystal with load capacitance of 12 pF is used. For other crystals, the external capacitors should be
chosen using the following equation, where CL is the crystal load capacitance: Crystal caps (pF) =(CL-12)x2.
So for a crystal with 16 pF load capacitance, two 8 pF caps should be used.
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