參數(shù)資料
型號： MK60DX256ZVLQ10
廠商： Freescale Semiconductor
文件頁數(shù)： 44/79頁
文件大?。?/td> 0K
描述： IC ARM CORTEX MCU 256KB 144LQFP
標準包裝： 300
系列： Kinetis
核心處理器： ARM? Cortex?-M4
芯體尺寸： 32-位
速度： 100MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，I²C，IrDA，SDHC，SPI，UART/USART，USB，USB OTG
外圍設備： DMA，I²S，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 100
程序存儲器容量： 256KB（256K x 8）
程序存儲器類型： 閃存
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.71 V ~ 3.6 V
數(shù)據(jù)轉換器： A/D 33x16b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 144-LQFP
包裝： 托盤
Table 30. 16-bit ADC with PGA characteristics (continued)
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
ENOB
Effective number
of bits
Gain=1, Average=4
Gain=64, Average=4
Gain=1, Average=32
Gain=2, Average=32
Gain=4, Average=32
Gain=8, Average=32
Gain=16, Average=32
Gain=32, Average=32
Gain=64, Average=32
11.6
7.2
12.8
11.0
7.9
7.3
6.8
7.5
13.4
9.6
14.5
14.3
13.8
13.1
12.5
11.5
10.6
—
bits
16-bit
differential
mode,fin=100Hz
SINAD
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (VCM) and the PGA gain.
4. Gain = 2PGAG
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 31. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
200
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
20
μA
VAIN
Analog input voltage
VSS – 0.3
—
VDD
V
VAIO
Analog input offset voltage
—
20
mV
VH
Analog comparator hysteresis1
CR0[HYSTCTR] = 00
CR0[HYSTCTR] = 01
CR0[HYSTCTR] = 10
CR0[HYSTCTR] = 11
—
5
10
20
30
—
mV
VCMPOh
Output high
VDD – 0.5
—
V
VCMPOl
Output low
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
50
200
ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
49
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