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參數(shù)資料
| 型號： | ML2036 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Serial Input Programmable Sine Wave Generator with Digital Gain Control |
| 中文描述： | 串行輸入可編程正弦波發(fā)生器數(shù)字增益控制 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 97K |
| 代理商： | ML2036 |
PRODUCT SPECIFICATION
ML2036
REV. 1.0.2 7/26/01
7
Functional Description
The ML2036 is composed of a programmable frequency
generator, a sine wave generator, a crystal oscillator, and
a serial digital interface. The ML2036 frequency and sine
wave generator functional block diagram is shown in
Figure 4.
Programmable Frequency Generator
The programmable frequency generator produces a digital
output whose frequency is determined by a 16-bit digital
word.
The frequency generator is composed of a phase accumula-
tor which is clocked at f
CLK IN
/4. The value stored in the
data latch is added to the phase accumulator every 4 cycles
of CLK IN. The frequency of the analog output is equal to
the rate at which the accumulator overflows and is given by
the equation:
The frequency resolution and the minimum frequency are
the same and is given by the following equation:
When f
CLK IN
= 12.352MHz,
f
MIN
= 1.5Hz (±0.75Hz).
Lower frequencies are obtained by using a lower input clock
frequency.
Due to the phase quantization nature of the frequency gener-
ator, spurious tones can be present in the output range of
–55dB relative to fundamental. The energy from these tones
is included in the signal to noise + distortion specification.
The frequency of these tones can be very close to the funda-
mental. Therefore, it is not practical to filter them out.
Sinewave Generator
The sinewave generator is composed of a sine look-up table,
a DAC, and an output smoothing filter. The sine look-up
table is addressed by the phase accumulator. The DAC is
driven by the output of the look-up table and generates a
staircase representation of a sine wave.
The output filter smoothes the analog output by removing the
high frequency sampling components. The resultant voltage
on V
OUT
is a sinusoid with the second and third harmonic
distortion components at least 45dB below the fundamental.
The ML2036 has a V
REF
input that can be tied to V
CC
or
generated from an external voltage. With the GAIN input
equal to a logic “1”, the sine wave peak-to-peak voltage is
equal to ±V
REF
; with the GAIN equal to a logic “0”, the
peak voltage is ±V
REF
/2. However, the overall output volt-
age swing is limited to no closer than 1.5V to either rail.
This means that to avoid clipping, V
REF
can only be tied to
V
CC
when GAIN is a logic “0”. The sinewave output is
referenced to AGND.
The analog section is designed to operate over a range from
DC to 50kHz. Due to slew rate limitations, the peak-to-peak
output voltage must be limited to V
OUT(P-P)
≤
(125kV x
Hz)/f
OUT
. For example, an output at 50kHz must be limited
to 2.5V
P-P
. V
OUT
can drive a 1k
, 100pF load and swing
to within 1.5V of V
CC
and V
SS
, provided the slew rate
limitations mentioned above are not exceeded.
The output offset voltage, V
OS
, is a function of the peak-to-
peak output voltage and is specified as:
For example, if V
OUT(P-P)
= 2.5V:
Crystal Oscillator
The crystal oscillator generates an accurate reference clock
for the programmable frequency generator. The internal
clock can be generated with a crystal or external clock.
If a crystal is used, it must be placed between CLK IN and
DGND of the ML2036. An on-chip crystal oscillator will
then generate the internal clock. No other external capacitors
or components are required. The crystal should be a parallel-
resonant type with a frequency between 3MHz to 12.4MHz.
It should be placed physically as close as possible to the
CLK IN and DGND.
An external clock can drive CLK IN directly if desired. The
frequency of this clock can be anywhere between 0 and
12MHz.
f
OUT
f
X D15
--------------------------------------------------------------
D0
–
)
2
=
(1)
f
MIN
f
2
----------------
=
V
OS MAX
)
2.5
-------------------------------------------
V
P
–
)
+
±
=
(3)
V
OS MAX
)
----------+
±
50mV
±
=
=
Figure 5. Serial Interface Timing.
SCK
SID
LATI
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
(2)
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參數(shù)描述 |
|---|---|
| ML2036CP | 功能描述:射頻接收器 DIP-14 SINE WAVE GEN RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel |
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| ML2036IP | 功能描述:射頻接收器 25khz Sinewave Gen DC Programmable RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel |
| ML2036IS | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Serial Input Programmable Sine Wave Generator with Digital Gain Control |
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