參數(shù)資料
型號(hào)： ML2111
廠商： Fairchild Semiconductor Corporation
英文描述： Universal Dual High Frequency Filter(通用雙通道高頻濾波器)
中文描述： 通用雙高頻濾波器（通用雙通道高頻濾波器）
文件頁(yè)數(shù)： 12/26頁(yè)
文件大?。?/td> 440K
代理商： ML2111
ML2111
12
f
CLK
/f
0
RATIO
The ML2111 is a sampled data filter and approximates
continuous time filters. The filter deviates from its ideal
continuous filter model when the (f
CLK
/f
0
) ratio decreases
and when the Qs are low.
f
0
′
Q PRODUCT RATIO
The f
0
′
Q product of the ML2111 depends on the clock
frequency and the mode of operation. The f
0
′
Q product
is mainly limited by the desired f
0
and Q accuracy for
clock frequencies below 1MHz in mode 1 and its
derivatives. If the clock to center frequency ratio is
lowered below 50:1, the f
0
′
Q product can be further
increased for the same clock frequency and for the same
Q value.
Mode 3, (Figure 23) and the modes of operation where R4
is finite, are "slower" than the basic mode 1. The resistor
R4 places the input op amp inside the resonant loop. The
finite GBW of this op amp creates an additional phase
shift and enhances the Q value at high clock frequencies.
OUTPUT NOISE
The wideband RMS noise on the outputs of the ML2111 is
nearly independent of the clock frequency, provided that
the clock itself does not become part of the noise. Noise
at the BP and LP outputs increases for high values of Q.
FILTER FUNCTION DEFINITIONS
Each filter of the ML2111, along with external resistors
and a clock, approximates second order filter functions.
These are tabulated below in the frequency domain.
1.
Bandpass function:
available at the bandpass output
pins (BP
A
, BP
B
), Figure 12.
s
Q
s
Q
G s
H
s
OBP
( )
=
+
+
w
w
w
0
2
0
0
2
(1)
where:
H
OBP
= Gain at
w
=
w
0
f
0
=
w
0
/2
p
. The center frequency of the complex pole
pair is f
0
. It is measured as the peak frequency of the
bandpass output.
Q = the Quality factor of the complex pole pair. It is
the ratio of f
0
to the -3dB bandwidth of the 2nd order
bandpass function. The Q is always measured at the
filter BP output.
FUNCTIONAL DESCRIPTION
POWER SUPPLIES
The analog (V
A+
) and digital (V
D+
) supply pins, in most
cases, are tied together and bypassed to AGND with
100nF and 10nF disk ceramic capacitors. The supply pins
can be bypassed separately if a high level of digital noise
exists. These pins are internally connected by the IC
substrate and should be biased from the same DC source.
The ML2111 operates from either a single supply from 4V
to 12V, or with dual supplies at ±2V to ±6V.
CLOCK INPUT PINS AND LEVEL SHIFT
With dual supplies equal to or higher than ±4.0V, the LSh
pin can be connected to the same potential as either the
AGND or the V
A
- pin. With single supply operation the
negative supply pins and LSh pin should be tied to the
system ground. The AGND pin should be biased half way
between V
A+
and V
A-
. Under these conditions the clock
levels are TTL or CMOS compatible. Both input clock
pins share the same level shift pin.
50/100/HOLD
Tying the 50/100/HOLD pin to the V
A+
and V
D+
pins
makes the filter operate in the 50:1 mode. Tying the pin
half way between V
A+
and V
A-
makes the filter operate in
the 100:1 mode. The input range for 50/100/HOLD is
either 2.5V ±0.5V with a total power supply range of 5V,
or 5V ±0.5V with a total power supply range of 10V.
When 50/100/HOLD is tied to the negative power supply
input, the filter operation is stopped and the bandpass and
lowpass outputs act as a sample/hold circuit which holds
the last sample.
S1
A
& S1
B
These voltage signal input pins should be driven by a
source impedance of less than 5k
W
. The S
1A
and S
1B
pins
can be used to feedforward the input signal for allpass
filter configurations (see modes 4 & 5) or to alter the
clock-to-center-frequency ratio (f
CLK
/f
0
) of the filter (see
modes 1b, 1c, 2a, & 2b). When these pins are not used
they should be tied to the AGND pin.
S
A/B
When S
A/B
is high, the S2 negative input of the voltage
summing device is tied to the lowpass output. When the
S
A/B
pin is connected to the negative supply, the S2 input
switches to ground.
AGND
AGND is connected to the system ground for dual supply
operation. When operating with a single positive supply
the analog ground pin should be biased half way between
V
A+
and V
A-
, and bypassed with a 100nF capacitor. The
positive inputs of the internal op amps and the reference
point of the internal switches are connected to the AGND
pin.
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