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參數(shù)資料
| 型號(hào)： | ML2111 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Universal Dual High Frequency Filter(通用雙通道高頻濾波器) |
| 中文描述： | 通用雙高頻濾波器（通用雙通道高頻濾波器） |
| 文件頁數(shù)： | 23/26頁 |
| 文件大?。?/td> | 440K |
| 代理商： | ML2111 |
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ML2111
23
OPERATION MODES
(Continued)
Mode 1a is a good choice when Butterworth filters are
desired since they have poles in a circle with the same f
0
.
Figure 31 shows an example of a 4th order, 100kHz
lowpass Butterworth filter clocked at 5MHz.
A monotonic passband response with a smooth transition
band results, showing the circuit's low sensitivity, even
though 1% resistors are used which results in an
approximate value of Q.
Figure 32 gives an example of a 4th order bandpass filter
implemented by cascading 2 sections, each with a Q of
10. This figure shows the amplitude response when f
CLK
=
7.5MHz, resulting in a center frequency of 150kHz and a
Q of 15.5.
Figure 33 uses mode 1d of a 4th order flter where each
section has a Q of 1, independent of resistor ratios. In this
mode, the input amplifier is outside the damping (Q)
loop. Therefore, its finite bandwidth does not degrade the
response at high frequency. This allows the amplifier to be
used as an anti-aliasing and continuous smoothing fliter
by placing a capacitor across R2.
OFFSETS
Switched capacitor integrators generally exhibit higher
input offsets than discrete RC integrators.
These offsets are mainly the charge injection of the
CMOS switchers into the integrating capacitors. The
internal op amp offsets also add to the overall offset
budget.Figure 35 shows half of the ML2111 filter with its
equivalent input offsets V
OS1
, V
OS2
, & V
OS3
.
The DC offset at the filter bandpass output is always equal
to V
OS3
. The DC offsets at the remaining two outputs
(Notch and LP) depend on the mode of operation and
external resistor ratios. Table 3 illustrates this.
It is important to know the value of the DC output offsets,
especially when the filter handles input signals with large
dynamic range. As a rule of thumb, the output DC offsets
increase when:
1. The Qs decrease
2. The ratio (f
CLK
/f
o
) increases beyond 100:1. This is done
by decreasing either the (R2/R4) or the R6/(R5 + R6)
resistor ratios.
+
+
Σ
15
5
V
OS1
3
2
1
4
+
V
OS3
V
OS2
(18)
(17)
+
+
+
+
(16)
(19)
(20)
Figure 35. Equivalent Input Offsets of of an ML2111 Filter.
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