參數(shù)資料
型號(hào): ML4790
廠商: Fairchild Semiconductor Corporation
英文描述: Adjustable Output, Low Ripple Boost Regulator(輸出可調(diào)、小波紋升壓穩(wěn)壓器)
中文描述: 可調(diào)輸出,低紋波升壓穩(wěn)壓器(輸出可調(diào),小波紋升壓穩(wěn)壓器)
文件頁(yè)數(shù): 4/10頁(yè)
文件大?。?/td> 192K
代理商: ML4790
4
ML4790
FUNCTIONAL DESCRIPTION
The ML4790 combines Pulse Frequency Modulation
(PFM) and synchronous rectification to create a boost
converter that is followed by a low dropout linear
regulator (LDO). This combination creates a low output
ripple boost converter that is both highly efficient and
simple to use.
The PFM regulator charges a single inductor for a fixed
period of time and then completely discharges before
another cycle begins, simplifying the design by
eliminating the need for conventional current limiting
circuitry. Synchronous rectification is accomplished by
replacing an external Schottky diode with an on-chip
PMOS device, reducing switching losses and external
component count.
The integrated LDO reduces the output ripple voltage to
less than 5mV peak-to-peak. Integrating the LDO along
with the PFM regulator allows the circuit to be optimized
for very high efficiency using a patented feedback
technique. It also allows the LDO to provide the
maximum ripple rejection over the operating frequency
range of the regulator.
A block diagram of the ML4790 is shown in Figure 2. The
PFM stage is comprised of Q1, Q2, A1, A2, the one shot,
the flip-flop, and externals L1 and C2. The LDO stage is
comprised of Q3, A3, the offset voltage control, and
external components R1, R2 and C
OUT
. Since the LDO
actually controls the operation of the PFM regulator, the
operation of the LDO stage will be covered first.
LDO OPERATION
The LDO stage operates as a linear regulator. A3 is the
error amplifier, which compares the output voltage
through the divider R1 and R2 to the reference, and Q3 is
the pass device. When the output voltage is lower than
desired, the output of A3 increases the gate drive of Q3,
which reduces the voltage drop across it and brings the
output back into regulation. Similarly, if the output voltage
is higher than desired, A3 adjusts the gate drive of Q3 for
more drop and the output is brought back into regulation.
450
400
350
300
250
200
150
100
V
O
(
0
I
OUT
(mA)
10
20
30
40
50
60
70
80
90 100
Figure 3. LDO V
OS
versus output current.
Also included in the LDO stage is an offset voltage
control. This circuit monitors the output current and
adjusts the offset voltage according the general
characteristic shown in Figure 3. The offset control
ensures that the PFM stage provides just enough
“overhead” voltage for the LDO stage to operate properly.
+
6
5
μ
s
ONE SHOT
R
S
L1
Q3
A2
A1
Q1
R1
C
OUT
+
+
5
C2
V
OS
= f (I
LOAD
)
+
A3
V
REF
R2
4
I
LOAD
Q2
3
C
FB
Figure 2. PFM Regulator and LDO Block Diagram
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參數(shù)描述
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