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參數(shù)資料
| 型號(hào)： | ML4819 |
| 廠商： | Fairchild Semiconductor Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Power Factor and PWM Controller “Combo” |
| 中文描述： | 功率因數(shù)和PWM控制器“組合” |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 269K |
| 代理商： | ML4819 |
ML4819
12
REV. 1.0 10/10/2000
OVERVOLTAGE PROTECTION (OVP) COMPONENTS
The OVP loop should be set so that there is no interaction
with the voltage control loop. Typically it should be set to
a level where the power components are safe to operate.
Ten to fifteen volts above V
OUT
seems to be adequate.
This sets the maximum transient output voltage to about
395V.
By choosing the high voltage side resistor of the OVP
circuit the same way as above i.e. R
7
= 356K then R
8
can
be calculated as:
R
V
R
V
V
V
395
k
5
V
V
k
REF
OVP
REF
8
7
5
356
4 564
.
=
×
=
×
=
(20)
Choose 4.53k
, 1%.
Note that R
5
, R
6
, R
7
and R
8
should be tight tolerance
resistors such as 1% or better.
OFF-LINE START-UP AND BIAS SUPPLY GENERATION
The Start-Up circuit in Figure 12 can be either a
“
bleed
resistor
”
(39k
, 2W) or the circuit shown in Figure 13. The
bleed resistor method offers advantage of simplicity and
lowest cost, but may yield excessive turn-on delay at low
line.
When the voltage on pin 15 (V
CC
) exceeds 16V, the IC
starts up. The energy stored on the C21 supplies the IC
with running power until the supplemental winding on T3
can provide the power to sustain operation.
PWM SECTION
The PWM section in Figure 12 is a two switch forward
converter, shown in Figure 14 below for clarity. This fully
clamped circuit eliminates the need for very high
voltage MOSFETs. Flyback topology is also possible with
the ML4819.
ENHANCEMENT CIRCUIT
The power factor enhancement circuit (inside the dotted
lines) in Figure 11 is described in Application Note 11. It
improves the power factor and lowers the input current
harmonics. Note that the circuit meets IEC1000-3-2
specifications (with the enhancement circuit installed) on
the harmonics by a large margin while correcting the
input power factor to better than 0.99 under most steady
state operating conditions.
R33
2k
R31
510k
R32
2k
Q5
2N2222
C21
0.1
D16
22V
V
REF
TO V
CC
OUT
IN
R30
4.3k
Q6
IRF821
D15
1N4001
START-UP
CIRCUIT
Figure 13. Start-Up Circuit
D12
D11
T2
T2
ML4819
T3
Q2
Q3
385VDC
Figure 14. Two-Switch Forward Converter
This regulator (Figure 12) uses current mode control.
Current is sensed through R24 and filtered for high
frequency noise and leading edge transient through T23
and C14. The main regulation loop is through PWM B. The
TL431 (U3) in the secondary serves as both the voltage
reference and error amplifier. Galvanic isolation is
provided by an optocoupler (U2) which provides a current
command signal on pin 8. Loop compensation is provided
by R29 and C20. The output voltage is set by:
V
R
R
OUT
=
+
2.
29
28
(21)
The control loop is compensated using standard
compensation techniques.
Current is limited to a threshold of 2A (1V on R24). The duty
cycle is limited in this circuit to below 50% to prevent
transformer (T3) core saturation. The maximum duty cycle
limit of 45% is set using a threshold of V
REF
/2 on pin 7.
the circuit in Figure 12 can be modified for voltage mode
operation by utilizing the slope current which appears on
pin 9 as show in figure 15 below.
The ramp amplitude appearing on pin 9 will be:
V
I
R( )
R
R
=
×
18
2
(22)
where R18 is the slope compensation resistor. Since this
circuit operates with a constant input voltage (as supplied
by the PFC section) voltage feed-forward is unnecessary.
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