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參數(shù)資料
| 型號(hào)： | ML4819 |
| 廠商： | Fairchild Semiconductor Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Power Factor and PWM Controller “Combo” |
| 中文描述： | 功率因數(shù)和PWM控制器“組合” |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 269K |
| 代理商： | ML4819 |
ML4819
REV. 1.0 10/10/2000
5
FUNCTIONAL DESCRIPTION
OSCILLATOR
The ML4819 oscillator charges the external capacitor (C
T
)
with a current (I
SET
) equal to 5/R
SET
. When the capacitor
voltage reaches the upper threshold, the comparator
changes state and the capacitor discharges to the lower
threshold through Q1. While the capacitor is discharging,
the clock provides a high pulse.
The oscillator period can be described by the following
relationship:
t
OSC
= t
RAMP
+ t
DEADTIME
where:
t
=C(Ramp Valley to Peak)
I
RAMP
SET
and:
t
C(Ramp Valley to Peak)
8.4mA - I
DEADTIME
SET
=
The maximum duty cycle of the PWM section can be
limited by setting a threshold on pin 7. when the C
T
ramp
is above the threshold at pin 7, the PWM output is held
off and the PWM flip-flop is set:
D
(V
-0.9)
3.4
where:
D
LIMIT
OSC
PIN7
×
D
LIMIT
= Desired duty cycle limit
D
OSC
= Oscillator duty cycle
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
UNDER-VOLTAGE LOCKOUT
Start-Up Threshold
15
16
17
V
Shut-Down Threshold
9
10
11
V
V
REF
Good Threshold
SUPPLY
4.4
V
Supply Current
Start-Up, V
CC
= 14V
Operating, T
J
= 25
°
C
0.6
1.2
mA
25
35
mA
Note 1:
Note 2:
Note 3:
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
V
CC
is raised above the Start-Up Threshold first to activate the IC, then returned to 15V.
PWM comparator bias currents are subtracted from this reading.
Figure 1. Oscillator Block Diagram
R
T
I
SET
C
T
CLOCK
DUTY CYCLE
20
10
I
SET
V
REF
5V
+5V
TO PWM
LATCH B
TO PWM
LATCHES
8.4mA
Q1
CLOCK
t
D
RAMP PEAK
RAMP VALLEY
C
T
7
+
–
+
–
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