參數(shù)資料
型號(hào): ML4828
廠商: Fairchild Semiconductor Corporation
英文描述: BiCMOS Phase Modulation/Soft Switching Controller(BiCMOS 相調(diào)制器/全橋軟開關(guān)控制器)
中文描述: BiCMOS工藝相位調(diào)制/軟開關(guān)控制器(BiCMOS工藝相調(diào)制器/全橋軟開關(guān)控制器)
文件頁(yè)數(shù): 6/11頁(yè)
文件大小: 187K
代理商: ML4828
6
ML4828
SETTING THE OSCILLATOR FREQUENCY
The ML4828 switching frequency is determined by the
charge and discharge times of the network connected to
the R
T
and C
T
pins. Figure 3 shows the relationships
between the internal clock and the charge and discharge
times.
t
DISCHARGE
RAMP PEAK
RAMP VALLEY
t
CHARGE
2.5V
1.25V
INTERNAL
CLOCK
Figure 3. Internal Oscillator Timing.
The frequency of the oscillator is:
f
t
t
OSC
CHARGE
DISCHARGE
=
+
1
(1)
The ramp peak is 2.5V and the ramp valley is 1.25V,
giving a ramp range of 1.25V. The charging current is set
externally through the resistor R
T
:
I
V
R
CHARGE
T
=
2 5
(2)
while the discharging current is fixed at 1.4 mA. The
charge and discharge times can be determined by:
t
C
V
I
C
R
CHARGE
T
CHARGE
T
T
=
×
=
×
2
1 25
.
(3)
t
C
I
DISCHARGE
V
C
V
mA
DISCHARGE
T
T
1 4
.
=
×
=
×
1 25
.
1 25
.
(4)
The oscillator frequency can then be found by substituting
the results of equations 3 and 4 into equation 1. This
frequency activates a T flip-flop which generates the
output pulses. The T flip-flop acts as a frequency divider
(
÷
2), so the output frequency will be:
f
f
OUT
OSC
2
=
(5)
ERROR AMPLIFIER
The ML4828 error amplifier has a 10MHz bandwidth and
a 10V/
μ
s slew rate. Figure 4 gives the Bode plot of the
error amplifier.
100
80
60
40
20
0
–20
180
135
90
45
0
100
1K
10K
100K
FREQUENCY
1M
10M
100M
G
P
GAIN
PHASE
Figure 4. Error Amplifier Open-Loop Gain
and Phase vs. Frequency.
OUTPUT DRIVERS
The ML4828 has four high-current CMOS output drivers,
each capable of 1A peak output current. These outputs
have been designed to quickly switch the gates of power
MOSFET transistors via a gate drive transformer. For higher
power applications, the outputs can be connected to
external MOSFET drivers.
The output phase delay times are set by charging an
internal 6.7pF capacitor up to the REF voltage (2.5V) via a
current that is externally programmed through R
A
and R
B
,
for the side A and side B drivers, respectively. The
charging current and delay time for side A are given by:
I
V
R
A
A
=
2 5
(6)
t
pF R
DA
A
=
6 7
(7)
The same equations can be applied to R
B
. For example,
with R
A
= 33k
:
t
pF
k
ns
DA
=
×
=
6 7
.
33
220
(8)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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