
7
ML4828
C
RST
+
–
R
RST
12
+
–
7
20
INHIBIT
OUTPUT
UNDER-VOLTAGE
LOCKOUT
CLOCK
2.5V
1.25V
RST
R
SENSE
R1
C1
V+
I
RST
S
Q
R
TERMINATE
PWM CYCLE
V+
I
1
I
SWITCH
I
LIM
1V
SS
C
SS
SOFT START TIME CONSTANT
During start up, the output voltage is much lower than the
steady state value. Without soft start circuitry, the error
amplifier output (EAO) would swing all the way to the
upper limit and the phase modulator would issue pulses
with full duty cycle, possibly causing output overshoot. To
ensure smooth start up, EAO (pin 8) is pulled low and
then gradually released through the charging of an
external soft start capacitor connected to SS (pin 7). The
soft start charging current is internally set at 25
μ
A. Hence,
EAO will rise with a time constant of:
dv
dt
A
C
SS
=
μ
25
(9)
For example, with C
SS
= 25
μ
F, the soft start rate of change
will be:
dv
dt
A
F
V
s
=
μ
μ
=
25
25
1
(10)
FAULT TIME CONSTANT AND RESTART DELAY
Figure 5 shows the internal circuitry and external
components involved in fault detection. During normal
operation, RST (pin 12) is discharged to ground through
the external resistor R
RST
. The I
LIM
comparator has a
threshold of 1V. R
SENSE
is selected so that the voltage
across it will be equal to the I
LIM
threshold at the
maximum desired I
SWITCH
current. When the voltage
across R
SENSE
exceeds 1V, the I
LIM
comparator trips,
terminating the present power cycle, and at the same time
activating the fault logic to turn on the 500
μ
A current
source I
RST
. This current charges the reset capacitor C
RST
.
For proper design, R
RST
should be very large (in the order
of 100k
). This will cause nearly all of the I
RST
current
(approximately 500
μ
A) to go into charging C
RST
at a rate of:
dv
dt
A
C
RST
=
μ
500
(11)
in volts per second. I
RST
will be turned off at the beginning
of the next clock cycle. If the current limit condition is
removed, RST will be gradually discharged to ground,
and normal operation resumes as shown in Figure 6.
Figure 5. Over-Current, Soft-Start, and Integrating Fault Detect Circuits.
Figure 6. I
LIM
and Resulting RC
RST
Waveforms During Load Surge.
1V
2.5V
V(PIN 20)
V(PIN 12)