參數(shù)資料
型號(hào)： ML63512A-XXXTP
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64
封裝： PLASTIC, TQFP-64
文件頁(yè)數(shù)： 29/33頁(yè)
文件大?。?/td> 281K
代理商： ML63512A-XXXTP
Semiconductor
ML63512A/63514A
4/32
FEDL63512A-03
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function. The power to the circuits corresponding
to the signal names inside
is supplied from VDDI (power supply for interface).
ROM
ML63512A: 4KW
ML63514A: 8KW
BUS
CON-
TROL
MIE
XT0
XT1
OSC0
OSC1
TBCCLK*
HSCLK*
OSC
CBR
EBR
L
C
G
Z
ALU
RA
A
IR
INSTRUCTION
DECODER
RAM
ML63512A: 128N
ML63514A: 256N
nX-4/250
RESETB
RST
VDDI
PC
H
Y
X
TIMING
CON-
TROL
SP
RSP
STACK
CAL: 16-level
REG: 16-level
TIMER
8bit
2
RXD*
TXC*
RXC*
TXD*
2
INT
SIO
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T0CK*
T1CK*
2
INT
I/O
PORT
P0.0-P0.3
P1.0-P1.3
P2.0-P2.3
P3.0-P3.3
P4.0-P4.3
P5.0-P5.3
P6.0-P6.3
=
P9.0-P9.3
=
PA.0-PA.3
=
4
INT
DATA
BUS
TBC
4
INT
1
VSS
MELODY
MD
1
INT
TST1B
TST
TST2B
P7.0-P7.3
INT
INPUT
PORT
P8.0-P8.3
OUTPUT
PORT
LDIN0*
Level
Detector
LDIN1*
CMPIN*
CMP
CMPREF*
VDDH
VDD
CB1
CB2
BACK-
UP
VDDL
VR
CPU CORE
=Port 6 (P6.0 to P6.3), Port 9 (P9.0 to P9.3) and Port A (PA.0 to PA.3) are provided for the 64-pin
packages and chips.
相關(guān)PDF資料
PDF描述
ML63512A-XXXTP 4-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64
ML63512A-XXXTB 4-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP48
ML63514A-XXXTP 4-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64
ML63514-XXXTP 4-BIT, MROM, MICROCONTROLLER, PQFP64
ML67Q5002LA 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PBGA144
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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