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參數(shù)資料
| 型號： | ML6510CQ-80 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 150K |
| 代理商： | ML6510CQ-80 |
ML6510
12
REV. 1.0 10/25/2000
Programming the ML6510
The configuration of the ML6510 is programmed by
loading 18 (ML6510-80) or 19 (ML6510-130) bits into the
configuration shift register. To load these bits, the user has
3 options: MAIN, AUX or ROM modes. Which mode is
used is determined by the logic level on the MDIN pin
when RESET is deasserted. If MDIN is tied high, the
ML6510 will assume AUX mode; if its tied low, ROM
mode. If MDIN is high-impedance (i.e. tied to the input of
an EEPROM), it will assume MAIN mode.
1. MAIN Mode
In this mode, the ML6510 will read the configuration bits
from an external serial EEPROM, such as the 93C46, using
the industry standard 3-wire serial I/O protocol. The serial
EEPROM should be a 1K organized in 64 x 16 bits and the
PACMan will read the configuration bits out of the two least
significant 16-bit words. To use this mode, simply connect
the EEPROM serial data input pin to MDIN (ML6510 pin
19), the EEPROM serial data output pin to MDOUT (ML6510
pin 20), and the EEPROM serial data clock pin to MCLK
(ML6510 pin 21) and CS pin for the EEPROM should be tied
to the RESET signal. After power up, when RESET is
deasserted, the ML6510 will automatically generate the
address and clock to read out the configuration bits. Refer
MAIN Mode waveform in Figure 5.
1K SERIAL
EEPROM
(64 X 16 BIT)
ML6510
CLOCK
OPCODES
ADDRESS
DATA
CLK
DATA IN
DATA OUT
MCLK
MDIN
MDOUT
RESET
ROMMSB
RESET
CS
MAIN Mode Configuration.
2. AUX Mode
When MDIN is tied to VCC, programming the ML6510
will occur via the AUX Mode. This mode shifts the
configuration bits into the shift register directly from the
MDOUT pin. The first 18 (ML6510-80) or 19 (ML6510-130)
clock rising edges provided externally on the MCLK pin
after RESET is deasserted will be used to load the shift
register data, which should be provided on the MDOUT
pin. See figure 6.
PROCESSOR
ML6510
CLOCK
VCC
DATA
MCLK
MDIN
MDOUT
ROMMSB
AUX Mode Configuration.
3. ROM Mode
When MDIN is tied to GND, programming the ML6510
will occur via the ROM Mode. This mode reads the
configuration bits directly from an on chip ROM. The
selection of one of the eight preset configuration codes is
accomplished by means of the pins ROMMSB, MCLK and
MDOUT as shown in Tables 1 and 2. The TEST mode
configuration (code 7) is enabled when the TEST bit is set.
In this mode the PLL is bypassed for low frequency
testing. Codes 0-2 are used when the ML6510 clock
inputs are driven from another PACMan’s reference clock
outputs. Code 3 is used when zero phase error is desired
between input and load clocks.
ROM
ADDRESS
BITS
ML6510
MCLK
MDOUT
MDIN
ROMMSB
ROM
8 X 19 BIT
TO SHIFT REGISTER
SERIAL DATA IN
ROM Mode Configuration.
01
02
03
04
05
06
07
08
09
10
11
12
25
MCLK
(Driven by
ML6510)
SB
1
OP1
1
MDIN
(Driven by
ML6510)
OP0
0
MDOUT
(Driven by
EEPROM)
D15
D14
D0
A5
0
A4
0
A3
0
A2
0
A1
0
A0
0
tM4
tM1
tM2
tM3
26
27
13
D13
D15
D14
2 bits at address 1
16 bits data at adddress 0
(28)
(D13)
(3 bits for ML6510-130)
Figure 5. MAIN Mode Waveforms.
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